MULTI-LEVEL MEMORY REPURPOSING

• US 20190043604A1
• Filed: 08/21/2018
• Published: 02/07/2019
• Est. Priority Date: 08/21/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Baca, Jim S., Tarango, Joseph
• Granted Patent: US 11,069,425 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/3034 where the computing system component is a storage system, e.g. DASD based or network based digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity

Abstract

An embodiment of a semiconductor apparatus may include technology to receive a request to modify a configuration of a persistent storage media, and repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request. Other embodiments are disclosed and claimed.

Claims

1. A storage system, comprising:

persistent storage media including multiple bits per cell;

a controller communicatively coupled to the persistent storage media; and

logic communicatively coupled to the controller and the persistent storage media to;

receive a request to modify a configuration of the persistent storage media, and

repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request.

2. The system of claim 1, wherein the logic is further to:

change a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell.

3. The system of claim 1, wherein the logic is further to:

identify a defective region of the persistent storage media; and

switch a sense mode for the defective region to contain less bits per cell.

4. The system of claim 3, wherein the logic is further to:

determine if the defective region is non-defective with the switched sense mode; and

repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode.

5. The system of claim 1, wherein the logic is further to:

evaluate blocks of the persistent storage media to identify blocks near cell failure;

pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell; and

repurpose the region of persistent storage media after a set of blocks has pooled a threshold number of blocks.

6. The system of claim 5, wherein the logic is further to:

provide estimated performance capability information based on the evaluation to a host; and

repurpose the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information.

7. The system of claim 1, wherein the persistent storage media comprises a solid state drive.

8. A semiconductor apparatus, comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to;

receive a request to modify a configuration of a persistent storage media, and

repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request.

9. The apparatus of claim 8, wherein the logic is further to:

change a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell.

10. The apparatus of claim 8, wherein the logic is further to:

identify a defective region of the persistent storage media; and

switch a sense mode for the defective region to contain less bits per cell.

11. The apparatus of claim 10, wherein the logic is further to:

determine if the defective region is non-defective with the switched sense mode; and

repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode.

12. The apparatus of claim 8, wherein the logic is further to:

evaluate blocks of the persistent storage media to identify blocks near cell failure;

pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell; and

repurpose the region of persistent storage media after a set of blocks has pooled a threshold number of blocks.

13. The apparatus of claim 12, wherein the logic is further to:

provide estimated performance capability information based on the evaluation to a host; and

repurpose the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information.

14. The apparatus of claim 8, wherein the persistent storage media comprises a solid state drive.

15. The apparatus of claim 8, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

16. A method of managing storage, comprising:

receiving a request to modify a configuration of a persistent storage media; and

repurposing a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request.

17. The method of claim 16, further comprising:

changing a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell.

18. The method of claim 16, further comprising:

identifying a defective region of the persistent storage media; and

switching a sense mode for the defective region to contain less bits per cell.

19. The method of claim 18, further comprising:

determining if the defective region is non-defective with the switched sense mode; and

repurposing the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode.

20. The method of claim 16, further comprising:

evaluating blocks of the persistent storage media to identify blocks near cell failure;

pooling one or more sets of blocks identified to be near cell failure based on the number of bits per cell; and

repurposing the region of persistent storage media after a set of blocks has pooled a threshold number of blocks.