SEMICONDUCTOR MEMORY DEVICE OF THREE-DIMENSIONAL STRUCTURE

• US 20190043872A1
• Filed: 12/28/2017
• Published: 02/07/2019
• Est. Priority Date: 08/07/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Oh, Sung-Lae, Kim, Dong-Hyuk, Jung, Soo-Nam
• Granted Patent: US 10,446,565 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor memory device includes first and second memory blocks each including conductive and dielectric layers alternately stacked over a semiconductor layer disposed over a substrate, and disposed adjacent to each other in a first direction; a dummy block disposed over the semiconductor layer, and provided between the first and second memory blocks; first pass transistors formed over the substrate below the first memory block, and coupled to conductive layers, respectively, of the first memory block; second pass transistors formed over the substrate below the second memory block, and coupled to conductive layers, respectively, of the second memory block; bottom global row lines between the first and second pass transistors and the semiconductor layer, and each coupled to one of the first pass transistors and one of the second pass transistors; and top global row lines formed over the dummy block, and coupled to the bottom global row lines.

Claims

1. A semiconductor memory device comprising:

first and second memory blocks disposed adjacent to each other in a first direction, each of the first and second memory blocks including a plurality of conductive layers and a plurality of dielectric layers alternately stacked over a semiconductor layer disposed over a substrate, and a plurality of channel structures passing through the conductive layers and the dielectric layers;

a dummy block disposed over the semiconductor layer, and provided between the first memory block and the second memory block;

a plurality of first pass transistors formed over the substrate and below the first memory block, and coupled to the respective conductive layers of the first memory block;

a plurality of second pass transistors formed over the substrate and below the second memory block, and coupled to the respective conductive layers of the second memory block;

a plurality of bottom global row lines formed in a bottom wiring layer below the semiconductor layer, and each coupled in common to one of the first pass transistors and one of the second pass transistors; and

top global row lines formed over the dummy block, and coupled to the respective bottom global row lines through first contact plugs, which pass through the dummy block.

2. The semiconductor memory device according to claim 1,

wherein the first and second memory blocks and the dummy block extend in a second direction, and

wherein one of the first pass transistors and one of the second pass transistors are disposed in a direction intersecting with the first direction and the second direction.

3. The semiconductor memory device according to claim 2, wherein each of the bottom global row lines comprises:

a first line pattern overlapping with the dummy block, extending in the second direction and coupled to one of the first contact plugs;

a second line pattern extending from one end of the first line pattern toward the first pass transistor in the first direction, and coupled to the first pass transistor through a second contact plug; and

a third line pattern extending from the other end of the first line pattern toward the second pass transistor in the first direction, and coupled to the second pass transistor through a third contact plug.

4. The semiconductor memory device according to claim 1,

wherein each of the first and second memory blocks comprises:

N (N is a natural number equal to or greater than

     2) number of stack groups stacked over the semiconductor layer, and each of the stack groups including a predetermined number of the conductive layers; and

N number stepped grooves corresponding to the respective stack groups and each exposing the predetermined number of the conductive layers of a corresponding stack group in a step-like shape, and

wherein the stepped grooves are disposed in a line along a second direction parallel to an extending direction of the first and second memory blocks and the dummy block.

5. The semiconductor memory device according to claim 4, wherein a width of the stepped grooves in the first direction is smaller than a maximum width, in the first direction, of the conductive layers included in the first and second memory blocks.

6. The semiconductor memory device according to claim 4, wherein the substrate comprises:

N number of contact regions corresponding to the stepped grooves; and

a plurality of cell regions disposed along the second direction with the contact regions interposed therebetween.

7. The semiconductor memory device according to claim 6, further comprising:

a plurality of page buffers formed over the substrate below the first and second memory blocks, and coupled to the first and second memory blocks through bit lines, and

wherein the page buffers are disposed in odd-numbered cell regions below the first memory block and even-numbered cell regions below the second memory block.

8. The semiconductor memory device according to claim 7, wherein the plurality of first pass transistors are disposed in the even-numbered cell regions below the first memory block, and the plurality of second pass transistors are disposed in the odd-numbered cell regions below the second memory block.

9. The semiconductor memory device according to claim 6, wherein the conductive layers of the first and second memory blocks are configured to traverse the contact regions and the cell regions without being cut along the second direction.

10. The semiconductor memory device according to claim 1, further comprising:

slits separating the first memory block and the dummy block from each other and separating the second memory block and the dummy block from each other.

11. The semiconductor memory device according to claim 1, wherein the dummy block has a structure in which a plurality of dummy conductive layers and a plurality of dielectric layers are alternately stacked.

12. The semiconductor memory device according to claim 11, wherein the dummy conductive layers are disposed at the same layers as the conductive layers of the first and second memory blocks.

13. The semiconductor memory device according to claim 12, wherein one of the conductive layers and one of the dummy conductive layers, both of which are disposed at the same layer among the conductive layers and the dummy conductive layers, are formed of the same material.

14. The semiconductor memory device according to claim 11, further comprising:

a sidewall dielectric layer surrounding outer walls of the first contact plugs, and isolating the first contact plugs and the dummy conductive layers from each other.

18. The semiconductor memory device according to claim 13, further comprising:

a sidewall dielectric layer formed over outer surfaces of the first contact plugs, and isolating the first contact plugs and the dummy block from each other and the first contact plugs and the semiconductor layer from each other.

15. A semiconductor memory device comprising:

a substrate including a plurality of cell regions arranged along a second direction different from a first direction, and contact regions disposed between the cell regions;

first and second memory blocks disposed adjacent to each other in the first direction, each including a plurality of conductive layers and a plurality of dielectric layers alternately stacked over a semiconductor layer formed over the substrate, and a plurality of channel structures passing through the conductive layers and the dielectric layers in the cell regions;

a dummy block disposed over the semiconductor layer between the first memory block and the second memory block;

first pass transistor units each including a predetermined number of first pass transistors coupled to conductive layers of the first memory block, and formed over even-numbered cell regions of the substrate to overlap with the first memory block;

second pass transistor units each including a predetermined number of second pass transistors coupled to conductive layers of the second memory block, and formed over odd-numbered cell regions of the substrate to overlap with the second memory block;

bottom global row lines formed in a bottom wiring layer below the semiconductor layer, and each coupled in common to one of the first pass transistors and one of the second pass transistors; and

a plurality of top global row lines formed over the dummy block, and coupled to the respective bottom global row lines through first contact plugs, which pass through the dummy block and the semiconductor layer.

16. The semiconductor memory device according to claim 15, wherein each of the bottom global row lines comprises:

a first line pattern overlapping with the dummy block, extending in the second direction and coupled to any one of the first contact plugs;

a second line pattern extending from one end of the first line pattern in the first direction, and coupled to one of the first pass transistors through a second contact plug; and

a third line pattern extending from the other end of the first line pattern in the first direction, and coupled to one of the second pass transistors through a third contact plug.

17. The semiconductor memory device according to claim 15, wherein the first pass transistor units or the second pass transistor units correspond to the respective contact regions and are disposed adjacent to corresponding contact regions, respectively, in the second direction.

19. The semiconductor memory device according to claim 15, wherein conductive layers of the first and second memory blocks are configured to traverse the contact regions and the cell regions without being cut along the second direction.