LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON

• US 20190043956A1
• Filed: 06/26/2018
• Published: 02/07/2019
• Est. Priority Date: 03/12/2015
• Status: Active Application

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: de Souza, Joel P., Fogel, Keith E., Reznicek, Alexander, Schepis, Dominic J.
• Application Number:
  US16/018,304
• Publication Number:
  US 20190043956A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06

Abstract

A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

Claims

1. A semiconductor structure comprising:

a stack of layers including a base silicon layer on a substrate, a thick silicon layer on the base silicon layer, and a thin silicon layer on the thick silicon layer, wherein the thin silicon layer is thinner than the thick silicon layer; and

a III-V layer directly on the thin silicon layer, wherein the III-V layer is relaxed, the thin silicon layer is strained, and the thick silicon layer is partially strained.

2. The structure of claim 1, wherein the thin silicon layer has a thickness between 10 nm and 50 nm and the thick silicon layer has a thickness between 100 nm and 200 nm.

3. The structure of claim 1, wherein a concentration of dopants within the thick silicon layer is greater than a concentration of dopants in the base and thin silicon layers.

4. The structure of claim 3, wherein the thick silicon layer has a boron concentration of 2E20 atoms per centimeter cubed and the thin silicon layer has a boron concentration of 2E18 atoms per centimeter cubed.

5. The structure of claim 1, wherein the partially strained thick silicon layer is a porous silicon layer.

6. The structure of claim 1, wherein the thin silicon layer is directly on the thick silicon layer.

7. The structure of claim 1, further comprising:

a buried oxide layer directly between the thin silicon layer and the base silicon layer.

8. The structure of claim 1, further comprising:

a buried oxide layer directly between the III-V layer and the base silicon layer.

9. A semiconductor structure comprising:

a stack of layers including a first semiconductor layer on a substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is thinner than the second semiconductor layer; and

a fourth semiconductor layer directly on the third semiconductor layer, wherein the fourth semiconductor layer is relaxed, the third semiconductor layer is strained, and the second semiconductor layer is partially strained.

10. The structure of claim 9, wherein a concentration of dopants within e second semiconductor layer is greater than a concentration of dopants in the first and third semiconductor layers.

11. The structure of claim 10, wherein the second semiconductor layer is silicon with a boron concentration of 2E20 atoms per centimeter cubed.

12. The structure of claim 9, wherein the partially strained second semiconductor layer is a porous semiconductor layer.

13. The structure of claim 9, wherein the third semiconductor layer is directly on the second semiconductor layer.

14. The structure of claim 9, wherein the third semiconductor layer is thinner than the fourth semiconductor layer.

15. The structure of claim 9, wherein the fourth semiconductor layer is a III-V semiconductor.