TRANSISTOR STRUCTURES HAVING A DEEP RECESSED P+ JUNCTION AND METHODS FOR MAKING SAME
First Claim
1. A method of forming a transistor device having at least one sidewall and an upper surface, comprising:
- providing a gate and a source on the upper surface;
providing at least one source region of a first conductivity type;
providing at least one well region of a second conductivity type adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth; and
etching at least a portion of the upper surface of the transistor device to a recess depth as measured from the upper surface.
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Accused Products
Abstract
A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
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Citations
25 Claims
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1. A method of forming a transistor device having at least one sidewall and an upper surface, comprising:
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providing a gate and a source on the upper surface; providing at least one source region of a first conductivity type; providing at least one well region of a second conductivity type adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth; and etching at least a portion of the upper surface of the transistor device to a recess depth as measured from the upper surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A transistor device comprising:
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a gate and a source on an upper surface of the transistor device; at least one source region of a first conductivity type within the transistor device; and at least one well region of a second conductivity type within the transistor device and adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth, wherein at least a portion of the upper surface of the transistor device includes an etched portion with a recess depth as measured from the upper surface. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method of forming a transistor device having at least one sidewall and an upper surface, comprising:
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providing a gate and a source on the upper surface; providing at least one source region of a first conductivity type; providing at least one well region of a second conductivity type adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth; etching at least a portion of the upper surface of the transistor device to a recess depth as measured from the upper surface; and forming an ohmic contact in the etched portion of the upper surface. - View Dependent Claims (25)
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Specification