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TRANSISTOR STRUCTURES HAVING A DEEP RECESSED P+ JUNCTION AND METHODS FOR MAKING SAME

  • US 20190043980A1
  • Filed: 10/01/2018
  • Published: 02/07/2019
  • Est. Priority Date: 12/28/2012
  • Status: Active Grant
First Claim
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1. A method of forming a transistor device having at least one sidewall and an upper surface, comprising:

  • providing a gate and a source on the upper surface;

    providing at least one source region of a first conductivity type;

    providing at least one well region of a second conductivity type adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth; and

    etching at least a portion of the upper surface of the transistor device to a recess depth as measured from the upper surface.

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