TRANSISTOR STRUCTURES HAVING A DEEP RECESSED P+ JUNCTION AND METHODS FOR MAKING SAME

• US 20190043980A1
• Filed: 10/01/2018
• Published: 02/07/2019
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun, Hull, Brett
• Granted Patent: US 10,886,396 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.

Claims

1. A method of forming a transistor device having at least one sidewall and an upper surface, comprising:

providing a gate and a source on the upper surface;

providing at least one source region of a first conductivity type;

providing at least one well region of a second conductivity type adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth; and

etching at least a portion of the upper surface of the transistor device to a recess depth as measured from the upper surface.

2. The method of claim 1, the method further comprising etching at least a portion of the at least one sidewall of the transistor device to the recess depth as measured from the upper surface.

3. The method according to claim 1, wherein a body of the transistor device comprises silicon carbide.

4. The method according to claim 1, wherein providing the at least one well region comprises implanting a P+ implanted junction.

5. The method according to claim 1, further comprising etching away at least a portion of the at least one source region.

6. The method according to claim 1, further comprising etching away at least a portion of the at least one well region.

7. The method according to claim 1, wherein the method does not include forming a termination area.

8. The method according to claim 1, wherein the depth is sufficient to result in an avalanche path to occur wholly within an active area of the transistor device instead of a termination device.

9. The method according to claim 1, wherein the transistor device further comprises a gate oxide on the gate and wherein the depth is sufficient to reduce an electrical field on the gate oxide.

10. The method according to claim 1, wherein the recess depth is about approximately 0.2 microns to about approximately 1.0 microns.

11. The method according to claim 1, wherein the recess depth is about approximately 0.2 microns to about approximately 0.4 microns.

12. The method according to claim 1, wherein the recess depth is about approximately 0.4 microns to about approximately 0.6 microns.

13. The method according to claim 1, wherein the recess depth is about approximately 0.6 microns to about approximately 0.8 microns.

14. A transistor device comprising:

a gate and a source on an upper surface of the transistor device;

at least one source region of a first conductivity type within the transistor device; and

at least one well region of a second conductivity type within the transistor device and adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth, wherein at least a portion of the upper surface of the transistor device includes an etched portion with a recess depth as measured from the upper surface.

15. The transistor device according to claim 14, wherein at least a portion of a sidewall of the transistor device includes an etched portion with a recess depth as measured from the upper surface.

16. The transistor device according to claim 14, wherein a body of the transistor device comprises silicon carbide.

17. The transistor device according to claim 14, wherein providing the at least one well region comprises a P+ implanted junction.

18. The transistor device according to claim 14, wherein the depth is sufficient to result in an avalanche path to occur wholly within an active area of the transistor device instead of a termination device.

19. The transistor device according to claim 14, wherein the transistor device further comprises a gate oxide on the gate and wherein the depth is sufficient to reduce an electrical field on the gate oxide.

20. The transistor device according to claim 14, wherein the recess depth is about approximately 0.2 microns to about approximately 1.0 microns.

21. The transistor device according to claim 14, wherein the recess depth is about approximately 0.2 microns to about approximately 0.4 microns.

22. The transistor device according to claim 14, wherein the recess depth is about approximately 0.4 microns to about approximately 0.6 microns.

23. The transistor device according to claim 14, wherein the recess depth is about approximately 0.6 microns to about approximately 0.8 microns.

24. A method of forming a transistor device having at least one sidewall and an upper surface, comprising:

providing a gate and a source on the upper surface;

providing at least one source region of a first conductivity type;

providing at least one well region of a second conductivity type adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth;

etching at least a portion of the upper surface of the transistor device to a recess depth as measured from the upper surface; and

forming an ohmic contact in the etched portion of the upper surface.

25. The method according to claim 24, further comprising etching at least a portion of the at least one sidewall of the transistor device to the recess depth as measured from the upper surface.