GOA CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE

• US 20190049768A1
• Filed: 09/15/2017
• Published: 02/14/2019
• Est. Priority Date: 08/14/2017
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Lv, Xiaowen, Chen, Shujhih
• Granted Patent: US 10,386,663 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/1343 Electrodes reflective electrodes G02F1/133553
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

The present invention involves a GOA circuit and a liquid crystal device. The GOA circuit comprises a plurality of cascaded GOA units. An N-th stage GOA unit controls charging of an N-th horizontal scanning line. The N-th stage GOA unit comprises a pull-high control unit, a pull-high unit, a pull-down unit, a pull-down sustain unit, and a boast capacitor (Cb). The pull-high unit, the pull-down sustain unit and the boast capacitor (Cb) are respectively connected with a first node (Q(N)) and a gate signal output terminal (G(N)) of the N-th stage GOA unit. The pull-high control unit and the pull-down unit are respectively connected with the first node (Q(N)) of the N-th stage GOA unit. The pull-down sustain unit comprises a first TFT (T61), a second TFT (T62), a third TFT (T64), a fourth TFT (T43), and a fifth TFT (T33). The present invention also provides a corresponding liquid crystal display device. The GOA circuit and the liquid crystal display device of the invention reduce the number of TFTs, reduce the layout space, which is beneficial for the narrow frame design of GOA product.

Claims

1. A GOA circuit, comprising:

a plurality of cascaded GOA units, wherein a N-th stage GOA unit controls charging of a N-th horizontal scanning line, the N-th stage GOA unit comprises a pull-high control unit, a pull-high unit, a pull-down unit, a pull-down sustain unit, and a boast capacitor;

the pull-high unit, the pull-down sustain unit and the boast capacitor are respectively connected with a first node and a gate signal output terminal of the N-th stage GOA unit, and the pull-high control unit and the pull-down unit are respectively connected with the first node of the N-th stage GOA unit;

the pull-down sustain unit comprises;

a first thin film transistor, a gate electrode of first thin film transistor being inputted with a low frequency clock signal, a source electrode and a drain electrode of first thin film transistor being respectively connected with a second node of the N-th stage GOA unit and inputted with the low frequency clock signal;

a second thin film transistor, a gate electrode of the second thin film transistor being connected with the first node of the N-th stage GOA unit, a source electrode and a drain electrode of the second thin film transistor being respectively connected with the second node of the N-th stage GOA unit and inputted with a constant-low-voltage signal;

a third thin film transistor, a gate electrode of the third thin film transistor being connected with a stage-transfer signal output terminal of the N-th stage GOA unit, a source electrode and a drain electrode of the third thin film transistor being respectively connected with the second node of the N-th stage GOA unit and inputted with the constant-low-voltage signal;

a fourth thin film transistor, a gate of the fourth thin film transistor being connected with the second node of the N-th stage GOA unit, a source electrode and a drain electrode of the fourth thin film transistor being respectively connected with the first node of the N-th stage GOA unit and inputted with the constant-low-voltage signal;

a fifth thin film transistor, a gate electrode of the fifth thin film transistor being connected with the second node of the N-th stage GOA unit, a source electrode and a drain electrode of the fifth thin film transistor being respectively connected with the gate signal output terminal of the N-th stage GOA unit and inputted with the constant-low-voltage signal.

2. The GOA circuit according to claim 1, wherein the pull-high control unit comprises a sixth thin film transistor, a gate of the sixth thin film transistor is connected with a stage-transfer signal output terminal of the (N−

m)th stage GOA unit, a source electrode and a drain electrode of the sixth thin film transistor are respectively connected with the first node of the N-th stage GOA unit and a gate signal output terminal of the (N−

m)th stage GOA unit, and m is a natural number.

3. The GOA circuit according to claim 2, wherein the gate of the sixth thin film transistor is connected with a stage-transfer output terminal of the (N−

4)th stage GOA unit, the source electrode and the drain electrode of the sixth thin film transistor are respectively connected with the first node of the N-th stage GOA unit and a gate signal output terminal of the (N−

4)th stage GOA unit.

4. The GOA circuit according to claim 1, wherein the pull-high unit comprises:

a seventh thin film transistor, a gate electrode of the seventh thin film transistor is connected with the first node of the N-th stage GOA unit, a source electrode and a drain electrode of the seventh thin film transistor are respectively connected with the gate signal output terminal of the N-th stage GOA unit and inputted with a clock signal;

an eighth thin film transistor, a gate electrode of the eighth thin film transistor is connected with the first node of the N-th stage GOA unit, a source electrode and a drain electrode of the eighth thin film transistor are respectively connected with the stage-transfer signal output terminal of the N-th stage GOA unit and inputted with the clock signal.

5. The GOA circuit according to claim 2, wherein the pull-high unit comprises a ninth thin film transistor, a gate of the ninth thin film transistor is connected with a gate signal output terminal of the (N+m)th stage GOA unit, a source electrode and a drain electrode of the ninth thin film transistor are respectively connected with the first node of the N-th stage GOA unit and the constant-low-voltage signal.

6. The GOA circuit according to claim 5, wherein the gate of the ninth thin film transistor is connected with a gate signal output terminal of the (N+4)th stage GOA unit, the source electrode and the drain electrode of the ninth thin film transistor are respectively connected with the first node of the N-th stage GOA unit and the constant-low-voltage signal.

7. The GOA circuit according to claim 1, wherein the low frequency clock signal is a constant-high-voltage signal.

8. A liquid crystal display device, comprising the GOA circuit according to claim 1.

9. A GOA circuit, comprising:

a plurality of cascaded GOA units, wherein a N-th stage GOA unit controls charging of a N-th horizontal scanning line, the N-th stage GOA unit comprises a pull-high control unit, a pull-high unit, a pull-down unit, a pull-down sustain unit, and a boast capacitor;

the pull-high unit, the pull-down sustain unit and the boast capacitor are respectively connected with a first node and a gate signal output terminal of the N-th stage GOA unit, and the pull-high control unit and the pull-down unit are respectively connected with the first node of the N-th stage GOA unit;

the pull-down sustain unit comprises;

a first thin film transistor, a gate electrode of first thin film transistor being inputted with a low frequency clock signal, a source electrode and a drain electrode of first thin film transistor being respectively connected with a second node of the N-th stage GOA unit and inputted with the low frequency clock signal;

a second thin film transistor, a gate electrode of the second thin film transistor being connected with the first node of the N-th stage GOA unit, a source electrode and a drain electrode of the second thin film transistor being respectively connected with the second node of the N-th stage GOA unit and inputted with a constant-low-voltage signal;

a third thin film transistor, a gate electrode of the third thin film transistor being connected with a stage-transfer signal output terminal of the N-th stage GOA unit, a source electrode and a drain electrode of the third thin film transistor being respectively connected with the second node of the N-th stage GOA unit and inputted with the constant-low-voltage signal;

a fourth thin film transistor, a gate of the fourth thin film transistor being connected with the second node of the N-th stage GOA unit, a source electrode and a drain electrode of the fourth thin film transistor being respectively connected with the first node of the N-th stage GOA unit and inputted with the constant-low-voltage signal;

a fifth thin film transistor, a gate electrode of the fifth thin film transistor being connected with the second node of the N-th stage GOA unit, a source electrode and a drain electrode of the fifth thin film transistor being respectively connected with the gate signal output terminal of the N-th stage GOA unit and inputted with the constant-low-voltage signal;

wherein the pull-high control unit comprises a sixth thin film transistor, a gate of the sixth thin film transistor is connected with a stage-transfer signal output terminal of the (N−

m)th stage GOA unit, a source electrode and a drain electrode of the sixth thin film transistor are respectively connected with the first node of the N-th stage GOA unit and a gate signal output terminal of the (N−

m)th stage GOA unit, and m is a natural number;

wherein the pull-high unit comprises;

a seventh thin film transistor, a gate electrode of the seventh thin film transistor is connected with the first node of the N-th stage GOA unit, a source electrode and a drain electrode of the seventh thin film transistor are respectively connected with the gate signal output terminal of the N-th stage GOA unit and inputted with a clock signal;

an eighth thin film transistor, a gate electrode of the eighth thin film transistor is connected with the first node of the N-th stage GOA unit, a source electrode and a drain electrode of the eighth thin film transistor are respectively connected with the stage-transfer signal output terminal of the N-th stage GOA unit and inputted with the clock signal;

wherein the pull-high unit comprises a ninth thin film transistor, a gate of the ninth thin film transistor is connected with a gate signal output terminal of the (N+m)th stage GOA unit, a source electrode and a drain electrode of the ninth thin film transistor are respectively connected with the first node of the N-th stage GOA unit and the constant-low-voltage signal;

wherein the low frequency clock signal is a constant-high-voltage signal.

10. The GOA circuit according to claim 9, wherein the gate of the sixth thin film transistor is connected with a stage-transfer output terminal of the (N−

4)th stage GOA unit, the source electrode and the drain electrode of the sixth thin film transistor are respectively connected with the first node of the N-th stage GOA unit and a gate signal output terminal of the (N−

4)th stage GOA unit.

11. The GOA circuit according to claim 9, wherein the gate of the ninth thin film transistor is connected with a gate signal output terminal of the (N+4)th stage GOA unit, the source electrode and the drain electrode of the ninth thin film transistor are respectively connected with the first node of the N-th stage GOA unit and the constant-low-voltage signal.