MEMORY CONTROLLER, MEMORY SYSTEM AND APPLICATION PROCESSOR COMPRISING THE MEMORY CONTROLLER

• US 20190050316A1
• Filed: 02/19/2018
• Published: 02/14/2019
• Est. Priority Date: 08/10/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Tae-hun, YU, Yong-sang, JO, Man-hwee, JOE, Min-young, KIM, Ji-woong, SEONG, Nak-hee
• Granted Patent: US 10,565,050 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/3093 Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
• CPC Class Codes: G06F 11/3442 for planning or managing the needed capacity
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors

Abstract

According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.

Claims

1. A memory controller configured to control a memory device including a plurality of memory pages, the memory controller comprising:

an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions; and

an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.

2. The memory controller of claim 1, wherein the ECC region manager is configured to store information on the ECC enable regions as region data.

3. The memory controller of claim 2, further comprising:

an ECC decider configured to receive the region data and determine whether to deliver data input to the memory controller to the ECC engine based on the region data.

4. The memory controller of claim 1, wherein, when data and data address are received from outside the memory controller and the ECC enable regions include the data address, the ECC engine performs the ECC operation on the received data, and

when the ECC disable regions include the data address, the ECC engine does not perform the ECC operation on the received data.

5. The memory controller of claim 1, wherein the ECC region manager is configured to receive, from outside the memory controller, a region decision control signal for identifying the ECC enable regions.

6. The memory controller of claim 1, further comprising

an ECC cache configured to store ECC data.

7. The memory controller of claim 6, wherein the ECC cache is configured to store the ECC data for each bank of the memory device.

8. A memory system comprising:

a memory device configured to include a plurality of memory pages; and

a memory controller configured to control the memory device,

wherein the memory controller is configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions and is configured to store ECC data and normal data in the ECC enable regions.

9. The memory system of claim 8, wherein each of ECC memory pages of the plurality of memory pages in the ECC enable regions comprises an ECC zone for storing the ECC data and a data zone for storing the normal data.

10. The memory system of claim 9, wherein a ratio of a capacity of bytes occupied by the ECC zone to a capacity of bytes occupied by the data zone is 1:

8.

11. The memory system of claim 9, wherein each of the ECC memory pages further comprises a dead zone that is neither the ECC zone nor the data zone.

12. The memory system of claim 11, wherein a capacity of each of the ECC memory pages is 2 KB.

the capacity of the data zone is 1792 bytes,

the capacity of the ECC zone is 224 bytes, and

a capacity of the dead zone is 32 bytes.

13. The memory system of claim 8, further comprising:

a memory module including a plurality of memory devices, at least one of the plurality of memory devices comprising the memory device,

the plurality of memory devices including,

a full-ECC memory device in which all memory pages are included in the ECC enable regions; and

a full-non ECC memory device in which all memory pages are included in the ECC disable regions.

14. An application processor comprising:

a processor, and

a memory controller configured to control an external memory device comprising a plurality of memory pages, the memory controller configured to receive data addresses from the processor, the memory controller configured to receive data from the external memory device or the processor, and the memory controller configured to determine, based on the data address, whether to perform ECC operation on the received data.

15. The application processor of claim 14, wherein the memory controller comprises:

an ECC engine configured to perform the ECC operation; and

an ECC decider configured to determine whether the ECC engine is to perform the ECC operation on the received data based on the data address,

wherein the ECC decider is configured to transmit the received data to he ECC engine in response to the received data indicating to perform the ECC operation.

16. The application processor of claim 15, wherein the memory controller further comprises:

an ECC region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions.

17. The application processor of claim 16, wherein the processor is configured to transmit to the memory controller a region decision control signal for identifying the ECC enable regions and the ECC disable regions.

18. The application processor of claim 16, wherein

the ECC region manager is configured to store information on the ECC enable regions as region data, and

the ECC decider is configured to determine whether the ECC engines performs the ECC operation on the received data based on the data address and the region data.

19. The application processor of claim 16, wherein the processor is configured to determine whether the data requires the ECC operation,

the processor assigns the data address to the ECC enable regions in response to the data requiring the ECC operation, and

the processor assigns the data address to the ECC disable regions in response to the data not requiring the ECC operation.

20. The application processor of claim 14, wherein the memory controller comprises an ECC cache configured to store ECC data.