ASYNCHRONOUS SINGLE FRAME UPDATE FOR SELF-REFRESHING PANELS

• US 20190051269A1
• Filed: 03/31/2018
• Published: 02/14/2019
• Est. Priority Date: 03/31/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kwa, Seh, Witter, Todd, Ansari, Nausheen, Sutaria, Gaurav
• Granted Patent: US 10,559,285 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2360/08 Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

Disclosed herein are techniques to provide both asynchronous frame updates and panel self-refresh in a single implementation. A platform can be arranged to provide frame updates asynchronously with the refresh rate of a connected panel while the connected panel can be arranged to self-refresh where no new updates are provided.

Claims

1. An apparatus, comprising:

a transmitter to send a frame to a panel via a display interconnect; and

a processor coupled to the transmitter, the processor to;

schedule the transmission of the frame to the panel at the beginning of one of a plurality of vertical blanking (VB) intervals asynchronously from the panels frame refresh, the frame to be transmitted to the panel via the transmitter and the display interconnect;

identify a first VB interval of the plurality of VB intervals where a frame is not scheduled to be transmitted to the panel; and

power down the display interconnect during the first VB interval.

2. The apparatus of claim 1, the processor to:

determine whether a full or a partial frame update is to be rendered within the current VB interval; and

schedule sending the full or partial frame update to the panel during the next VB interval based on a determination that the full or partial frame update is to be rendered within the current VB interval.

3. The apparatus of claim 2, the processor to:

determine whether a graphics processing unit (GPU) will complete rendering the full or partial frame update a selected time before the current VB interval ends; and

cause the GPU to enter a lower power state upon completion of rendering the full or partial frame update based on a determination that the GPU will complete rendering the full or partial frame update a selected time before the current VB interval ends.

4. The apparatus of claim 2, the processor to shut down the display interconnect based on a determination that the full or partial frame update is not to be rendered within the current VB interval.

5. The apparatus of claim 2, the processor to:

determine whether the display interconnect is shut down; and

power up the display interconnect and synchronize the transmitter with the panel based on a determination that the display interconnect is shut down.

6. The apparatus of claim 1, the processor to increase the VB interval a threshold amount up to a maximum VB interval allowed by the panel.

7. The apparatus of claim 1, the transmitter to send the frame to the panel in accordance with the Embedded Display Port (eDP) Standard v 1.4, published in February 2015 and promulgated by the Video Electronics Standards Association (VESA).

8. The apparatus of claim 1, comprising a display interface coupled to the transmitter, the display interface to couple to the display interconnect.

9. The apparatus of claim 8, the display interface comprising a display port interface or an embedded display port interface.

10. A method comprising:

scheduling the transmission of a frame to a panel at the beginning of one of a plurality of vertical blanking (VB) intervals asynchronously from a refresh rate of the panel, the frame to be transmitted to the panel via a transmitter and a display interconnect coupled to the panel;

identify a first VB interval of the plurality of VB intervals; and

power down the display interconnect during the first VB interval.

11. The method of claim 10, identify the first VB interval based at least in part on a frame not scheduled to be transmitted to the panel during the first VB interval.

12. The method of claim 11, comprising:

determining whether a full or a partial frame update is to be rendered within the current VB interval;

scheduling sending the full or partial frame update to the panel during the next VB interval based on a determination that the full or partial frame update is to be rendered within the current VB interval;

determining whether a graphics processing unit (GPU) will complete rendering the full or partial frame update a selected time before the current VB interval ends; and

causing the GPU to enter a lower power state upon completion of rendering the full or partial frame update based on a determination that the GPU will complete rendering the full or partial frame update a selected time before the current VB interval ends.

13. The method of claim 12, comprising shutting down the display interconnect based on a determination that the full or partial frame update is not to be rendered within the current VB interval.

14. The method of claim 12, comprising:

determining whether the display interconnect is shut down; and

powering up the display interconnect and synchronizing the transmitter with the panel based on a determination that the display interconnect is shut down.

15. The method of claim 11, comprising increasing the VB interval a threshold amount up to a maximum VB interval allowed by the panel.

16. The method of claim 11, comprising sending the frame to the panel in accordance with the Embedded Display Port (eDP) Standard v 1.4, published in February 2015 and promulgated by the Video Electronics Standards Association (VESA).

17. The method of claim 11, the display interface comprising a display port interface or an embedded display port interface.

18. At least one machine-readable storage medium comprising instructions that when executed by a processor at a platform coupled to a panel via a display interconnect, cause the processor to:

schedule the transmission of the frame to the panel at the beginning of one of a plurality of vertical blanking (VB) intervals asynchronously from the panels frame refresh, the frame to be transmitted to the panel via the transmitter and the display interconnect;

identify a first VB interval of the plurality of VB intervals where a frame is not scheduled to be transmitted to the panel; and

power down the display interconnect during the first VB interval.

19. The at least one machine-readable storage medium of claim 18, comprising instructions that further cause the processor to:

determine whether a full or a partial frame update is to be rendered within the current VB interval; and

schedule sending the full or partial frame update to the panel during the next VB interval based on a determination that the full or partial frame update is to be rendered within the current VB interval.

20. The at least one machine-readable storage medium of claim 19, comprising instructions that further cause the processor to:

determine whether a graphics processing unit (GPU) at the platform will complete rendering the full or partial frame update a selected time before the current VB interval ends; and

cause the GPU to enter a lower power state upon completion of rendering the full or partial frame update based on a determination that the GPU will complete rendering the full or partial frame update a selected time before the current VB interval ends.

21. The at least one machine-readable storage medium of claim 18, comprising instructions that further cause the processor to shut down the display interconnect based on a determination that the full or partial frame update is not to be rendered within the current VB interval.

22. The at least one machine-readable storage medium of claim 18, comprising instructions that further cause the processor to:

determine whether the display interconnect is shut down; and

power up the display interconnect and synchronizing the transmitter with the panel based on a determination that the display interconnect is shut down.

23. The at least one machine-readable storage medium of claim 18, comprising instructions that further cause the processor to increase the VB interval a threshold amount up to a maximum VB interval allowed by the panel.

24. The at least one machine-readable storage medium of claim 18, comprising instructions that further cause the transmitter to send the frame in accordance with the Embedded Display Port (eDP) Standard v 1.4, published in February 2015 and promulgated by the Video Electronics Standards Association (VESA).

25. The at least one machine-readable storage medium of claim 18, the display interconnect comprising a display port interconnect or an embedded display port interconnect.