QUBIT NETWORK NON-VOLATILE IDENTIFICATION

• US 20190051810A1
• Filed: 10/08/2018
• Published: 02/14/2019
• Est. Priority Date: 05/18/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brink, Markus, Hertzberg, Jared B., Rosenblatt, Sami
• Granted Patent: US 10,529,907 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G01R 33/34023 Superconducting RF coils
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: G11C 11/44 using super-conductive elements, e.g. cryotron
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 2223/54446 Wireless electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H03H 11/02 Multiple-port networks
• CPC Class Codes: H04L 63/0876 based on the identity of the terminal or configuration, e.g. MAC address, hardware or software configuration or device fingerprint
• CPC Class Codes: H10N 60/0912 of Josephson-effect devices
• CPC Class Codes: H10N 60/12 Josephson-effect devices
• CPC Class Codes: H10N 60/805 for Josephson-effect devices
• CPC Class Codes: H10N 60/815 for Josephson-effect devices
• CPC Class Codes: H10N 60/82 Current path
• CPC Class Codes: H10N 69/00 Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Abstract

A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Claims

1. A method of identifying a superconducting chip comprising:

receiving first resonant frequencies and second resonant frequencies, the first resonant frequencies being in a predefined frequency band, the second resonant frequencies being outside of the predefined frequency band, wherein the second resonant frequencies each have an expected frequency location in a different predefined frequency band;

correlating a first representation to each of the first resonant frequencies in the predefined frequency band; and

correlating a second representation to the expected frequency location for each of the second resonant frequencies, wherein a combination of the first and second representations identify the superconducting chip.

2. The method of claim 1, wherein the first representation is selected from the group consisting of a number, a symbol, and a letter.

3. The method of claim 2, wherein the second representation is selected from the group consisting of another number, another symbol, and another letter.

4. The method of claim 1, wherein the superconducting chip comprises resonant units having resonant frequencies, the resonant units comprising Josephson junctions;

and

wherein one or more of the Josephson junctions are configured to have a shorted tunnel barrier.

5. The method of claim 4, wherein the shorted tunnel barrier causes an increase in the resonant frequencies for the resonant units having the shorted tunnel barrier.

6. The method of claim 4, wherein some of the Josephson junctions have a tunnel barrier that is not shorted.

7. The method of claim 4, wherein the resonant frequencies are designed to fall within a predefined frequency band for each of the resonant units having no shorted tunnel barrier in the Josephson junctions.

8. The method of claim 7, wherein the resonant frequencies for the resonant units having the shorted tunnel barrier are designed to fall outside of the predefined frequency band.

9. The method of claim 4, wherein the Josephson junctions having the shorted tunnel barrier are predefined in advance in order to provide a predefined chip identification.

10. The method of claim 4, wherein the Josephson junctions are structured to have a first configuration or a second configuration.

11. The method of claim 10, wherein the first configuration is a non-shorted Josephson junction, the non-shorted Josephson junction having a tunnel barrier defined as not being shorted.

12. The method of claim 11, wherein the second configuration is a shorted Josephson junction, the shorted Josephson junction being defined as having the shorted tunnel barrier.

13. The method of claim 10, wherein a combination of the first configuration and the second configuration defines a binary representation.

14. The method of claim 10, wherein a combination of the resonant frequencies, associated with the first configuration and the second configuration, defines a binary representation.

15. The method of claim 4, wherein the resonant units having the Josephson junctions without the shorted tunnel barrier are configured to be read out as a first binary number.

16. The method of claim 15, wherein the resonant units having the one or more of the Josephson junctions with the shorted tunnel barrier are configured to be read out as a second binary number.

17. A method of causing identification of a superconducting chip comprising:

causing the superconducting chip to provide resonant frequencies from resonant units, the resonant frequencies including first resonant frequencies within a predefined frequency band and second resonant frequencies outside of the predefined frequency band, wherein the second resonant frequencies each have an expected frequency location in a different predefined frequency band;

correlating a first representation to each of the first resonant frequencies in the predefined frequency band and a second representation to the expected frequency location for each of the second resonant frequencies, wherein a combination of the first and second representations is a present identification of the superconducting chip; and

determining that a previously stored identification is a match to the present identification of the superconducting chip.

18. The method of claim 17, further comprising in response to the match, identifying the superconducting chip having the present identification from different chips having different identifications.

19. The method of claim 17, wherein the superconducting chip comprises resonant units having the resonant frequencies, the resonant units comprising Josephson junctions.

20. The method of claim 19, wherein one or more of the Josephson junctions are configured to have a shorted tunnel barrier.