METHOD AND APPARATUS FOR DETERMINING A CLOCK FREQUENCY FOR AN ELECTRONIC PROCESSOR

• US 20190052226A1
• Filed: 08/08/2017
• Published: 02/14/2019
• Est. Priority Date: 08/08/2017
• Status: Active Grant

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola Solutions, Inc.
• Inventors: Rozental, Mark, Tordjman, Claudine, Young, Richard S., Vallach, Uri
• Granted Patent: US 10,637,397 B2
• Time in Patent Office: Days
• CPC Class Codes: H01R 13/646 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match non-coaxed protective earth or shield arrangements H01R13/648; coaxed connectors specially adapted for high frequency H01R24/40
• CPC Class Codes: H03B 5/1271 the frequency being controlled by a control current, i.e. current controlled oscillators
• CPC Class Codes: H03B 5/36 active element in amplifier being semiconductor device H03B5/323, H03B5/326 , H03B5/38 take precedence
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 1/02 against variations of temperature only
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

Claims

1. A method for determining a clock frequency for an electronic processor receiving a clock signal from a clock generator, the method comprising:

programming, using a tuning logic controller, a phase locked loop of the clock generator to a first frequency;

determining an integrated circuit process corner of the electronic processor;

determining a second frequency based on the integrated circuit process corner; and

programming, using the tuning logic controller, the phase locked loop to the second frequency.

2. The method of claim 1, further comprising:

determining, using a temperature sensor, an ambient temperature, wherein determining the integrated circuit process corner is based on the ambient temperature.

3. The method of claim 1 wherein the phase locked loop has a tuning voltage associated with a programmed frequency of the phase locked loop and wherein determining the integrated circuit process corner further comprises:

setting a low voltage threshold to a first value from a list of voltages;

setting a high voltage threshold to a second value from the list of voltages;

adjusting the low voltage threshold higher to a first voltage based on the tuning voltage;

adjusting the high voltage threshold lower to a second voltage based on the tuning voltage, the first voltage and the second voltage defining a voltage range of the tuning voltage for the first frequency;

determining the integrated circuit process corner based on the voltage range of the tuning voltage for the first frequency.

4. The method of claim 3, wherein the phase locked loop includes a phase detector receiving a reference signal, a charge pump coupled to the phase detector and configured to output the tuning voltage, and a voltage controlled oscillator receiving the tuning voltage and configured to generate the clock signal based on the tuning voltage, the method further comprising:

setting a second low voltage threshold to the first value from the list of voltages;

setting a second high voltage threshold to the second value from the list of voltages;

adjusting the second low voltage threshold higher to a third voltage based on the tuning voltage;

adjusting the second high voltage threshold lower to a fourth voltage based on the tuning voltage, the third voltage and the fourth voltage defining a voltage range of the tuning voltage for the second frequency;

determining a gain of the voltage controlled oscillator based on the first frequency, the second frequency, an average of the voltage range of the tuning voltage for the first frequency, and an average of the voltage range of the second frequency; and

programming a charge pump current corresponding to the gain of the voltage controlled oscillator to achieve desired phase locked loop bandwidth.

5. The method of claim 1, wherein the phase locked loop includes a digitally controlled oscillator and receives a reference signal from a crystal oscillator of the clock generator, wherein the digitally controlled oscillator provides a feedback signal to the phase locked loop, wherein determining the integrated circuit process corner further comprises:

setting a control word of the phase locked loop to a minimum value;

setting a divider of the phase locked loop to a first divider value corresponding to a first difference in frequency between the reference signal and the feedback signal;

determining a minimum frequency of the feedback signal based on the minimum value;

setting the control word of the phase locked loop to a maximum value;

setting the divider of the phase locked loop to a second divider value corresponding to a second difference in frequency between the reference signal and the feedback signal;

determining a maximum frequency of the feedback signal based on the maximum value; and

determining the integrated circuit process corner based on the minimum frequency and the maximum frequency.

6. The method of claim 5, wherein determining the minimum frequency of the feedback signal and the maximum frequency of the feedback signal further comprises:

counting a first plurality of cycles in the reference signal for a predetermined period of time; and

counting a second plurality of cycles in the feedback signal for the predetermined period of time.

7. A clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor, the clock generator comprising:

a crystal oscillator producing a reference signal;

a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal; and

a tuning logic controller electrically coupled to the phase locked loop, the tuning logic controller configured to;

program the phase locked loop to a first frequency,

determine an integrated circuit process corner of the electronic processor connected to the clock generator,

determine a second frequency based on the integrated circuit process corner; and

program the phase locked loop to the second frequency.

8. The clock generator of claim 7, further comprising:

a temperature sensor detecting a an ambient temperature, wherein the tuning logic controller is further configured to determine the integrated circuit process corner based on the ambient temperature.

9. The clock generator of claim 7, wherein the phase locked loop includes:

a phase detector receiving the reference signal;

a charge pump coupled to the phase detector and configured to output a tuning voltage; and

a voltage controlled oscillator receiving the tuning voltage and configured to generate the clock signal based on the tuning voltage.

10. The clock generator of claim 9, further comprising:

a low comparator electrically coupled to the tuning logic controller and receiving the tuning voltage, the low comparator having a low voltage threshold; and

a high comparator electrically coupled to the tuning logic controller and receiving the tuning voltage, the high comparator having a high voltage threshold;

wherein the tuning logic controller for determining the integrated circuit process corner is further configured to;

set the low voltage threshold to a first value from a list of voltages;

set the high voltage threshold to a second value from the list of voltages;

adjust the low voltage threshold higher to a first voltage based on the tuning voltage;

adjust the high voltage threshold lower to a second voltage based on the tuning voltage, the first voltage and the second voltage defining a voltage range of the tuning voltage for the first frequency;

determine the integrated circuit process corner based on the voltage range of the tuning voltage for the first frequency.

11. The clock generator of claim 10, wherein after programming the phase locked loop to the second frequency, the tuning logic controller is further configured to:

set the low voltage threshold to the first value from the list of voltages;

set the high voltage threshold to the second value from the list of voltages;

adjust the low voltage threshold higher to a third voltage based on the tuning voltage;

adjust the high voltage threshold lower to a fourth voltage based on the tuning voltage, the third voltage and the fourth voltage defining a voltage range of the tuning voltage for the second frequency;

determine a gain of the voltage controlled oscillator based on the first frequency, the second frequency, an average of the voltage range of the tuning voltage for the first frequency, and an average of the voltage range of the tuning voltage for the second frequency; and

program a charge pump current of the charge pump corresponding to the gain of the voltage controlled oscillator to achieve desired phase locked loop bandwidth.

12. The clock generator of claim 7, wherein the phase locked loop includes:

a phase detector receiving the reference signal;

a time-to-digital converter coupled to the phase detector and converts an output of the phase detector to a control word; and

a digitally controlled oscillator receiving the control word and configured to generate the clock signal based on the control word, wherein the clock signal is provided as a feedback signal to the phase detector.

13. The clock generator of claim 12, further comprising:

a measurement system coupled to the phase locked loop and the tuning logic controller and counts a first plurality of cycles in the reference signal and a second plurality of cycles in the feedback signal, and

wherein the tuning logic controller for determining the integrated circuit process corner is further configured to;

set the control word to a minimum value;

set a divider of the phase locked loop to a first divider value corresponding to a first difference in frequency between the reference signal and the feedback signal;

determine, using the measurement system, a minimum frequency of the feedback signal based on the minimum value;

set the control word to a maximum value;

set the divider of the phase locked loop to a second divider value corresponding to a second difference in frequency between the reference signal and the feedback signal;

determine, using the measurement system, a maximum frequency of the feedback signal based on the maximum value; and

determine the integrated circuit process corner based on the minimum frequency and the maximum frequency.

14. A portable communications device, comprising:

an electronic processor;

a clock generator providing a clock signal to the electronic processor, the clock generator including;

a crystal oscillator producing a reference signal;

a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal; and

a tuning logic controller electrically coupled to the phase locked loop, the tuning logic controller configured to;

program the phase locked loop to a first frequency,

determine an integrated circuit process corner of the electronic processor,

determine a second frequency based on the integrated circuit process corner; and

program the phase locked loop to the second frequency.

15. The portable communications device of claim 14, further comprising:

a temperature sensor detecting a an ambient temperature, wherein the tuning logic controller is further configured to determine the integrated circuit process corner based on the ambient temperature.

16. The portable communications device of claim 14, wherein the phase locked loop includes:

a phase detector receiving the reference signal;

a charge pump coupled to the phase detector and configured to output a tuning voltage;

a voltage controlled oscillator receiving the tuning voltage and configured to generate the clock signal based on the tuning voltage;

a low comparator electrically coupled to the tuning logic controller and receiving the tuning voltage, the low comparator having a low voltage threshold; and

a high comparator electrically coupled to the tuning logic controller and receiving the tuning voltage, the high comparator having a high voltage threshold;

wherein the tuning logic controller for determining the integrated circuit process corner is further configured to;

set the low voltage threshold to a first value from a list of voltages;

set the high voltage threshold to a second value from the list of voltages;

adjust the low voltage threshold higher to a first voltage based on the tuning voltage;

adjust the high voltage threshold lower to a second voltage based on the tuning voltage, the first voltage and the second voltage defining a voltage range of the tuning voltage for the first frequency;

determine the integrated circuit process corner based on the voltage range of the tuning voltage for the first frequency.

17. The portable communications device of claim 16, wherein after programming the phase locked loop to the second frequency, the tuning logic controller is further configured to:

set the low voltage threshold to the first value from the list of voltages;

set the high voltage threshold to the second value from the list of voltages;

adjust the low voltage threshold higher to a third voltage based on the tuning voltage;

adjust the high voltage threshold lower to a fourth voltage based on the tuning voltage, the third voltage and the fourth voltage defining a voltage range of the tuning voltage for the second frequency;

determine a gain of the voltage controlled oscillator based on the first frequency, the second frequency, an average of the voltage range of the first frequency, and an average of the voltage range of the second frequency; and

program a charge pump current of the charge pump corresponding to the gain of the voltage controlled oscillator to achieve desired phase locked loop bandwidth.

18. The portable communications device of claim 14, wherein the phase locked loop includes:

a phase detector receiving the reference signal;

a time-to-digital converter coupled to the phase detector and converts an output of the phase detector to a control word;

a digitally controlled oscillator receiving the control word and configured to generate the clock signal based on the control word, wherein the clock signal is provided as a feedback signal to the phase detector; and

a measurement system coupled to the phase locked loop and the tuning logic controller and counts a first plurality of cycles in the reference signal and a second plurality of cycles in the feedback signal, and

wherein the tuning logic controller for determining the integrated circuit process corner is further configured to;

set the control word to a minimum value;

set a divider of the phase locked loop to a first divider value corresponding to a first difference in frequency between the reference signal and the feedback signal;

determine, using the measurement system, a minimum frequency of the feedback signal based on the minimum value;

set the control word to a maximum value;

set the divider of the phase locked loop to a second divider value corresponding to a second difference in frequency between the reference signal and the feedback signal;

determine, using the measurement system, a maximum frequency of the feedback signal based on the maximum value; and

determine the integrated circuit process corner based on the minimum frequency and the maximum frequency.