SEMICONDUCTOR CIRCUIT
First Claim
Patent Images
1. A semiconductor circuit comprising:
- a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal;
a second logic gate that receives inputs of a first input signal and the feedback signal, and performs a second logical operation; and
a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a third logical operation to output the feedback signal.
0 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.
0 Citations
16 Claims
-
1. A semiconductor circuit comprising:
-
a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal; a second logic gate that receives inputs of a first input signal and the feedback signal, and performs a second logical operation; and a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a third logical operation to output the feedback signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A semiconductor circuit comprising:
-
a first logic gate that receives inputs of a second input signal, a clock signal and a feedback signal and performs a second sub-logical operation to output a first output signal, the second input signal being generated by performing a first sub-logical operation on an inverted signal of the first output signal and a first input signal; a second logic gate that receives inputs of the first input signal and the feedback signal to perform a first logical operation; and a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a second logical operation to output the feedback signal. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
-
Specification