METHOD FOR MAXIMIZING FREQUENCY WHILE CHECKING DATA INTEGRITY ON A PHYSICAL INTERFACE BUS

• US 20190056880A1
• Filed: 08/17/2017
• Published: 02/21/2019
• Est. Priority Date: 08/17/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: TZAFRIR, Yonatan, ZEHAVI, Mordekhay, ASFUR, Mahmud
• Granted Patent: US 10,466,920 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06K 2207/1018 Source control
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer

Abstract

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

Claims

1. A method comprising:

in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,

performing, by the controller, a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern;

performing a read operation on the memory through the memory interface at a second frequency to determine a second data pattern; and

changing the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

2. The method of claim 1, wherein changing the first frequency comprises:

in response to the first pattern being equal to the second pattern,

increasing the first frequency by a predetermined amount.

3. The method of claim 1, wherein changing the first frequency comprises:

in response to the first pattern being not equal to the second pattern,

decreasing the first frequency by the predetermined amount.

4. The method of claim 1, wherein the predetermined amount is based on a setup and hold time required by the read operation.

5. The method of claim 4, wherein the first pattern is not equal to the second pattern and the setup and hold time determine a maximum frequency of operation of the host interface.

6. The method of claim 1, wherein the predetermined amount is based on at least one of a change in operating voltage, operating temperature, or load of the host interface.

7. The method of claim 1, further comprising terminating said changing when the first frequency is equal to a maximum operating frequency.

8. The method of claim 1, wherein said changing occurs during an idle time of the host interface.

9. The method of claim 1, wherein said changing occurs a predetermined amount of time after the completion of the controller servicing an interrupt.

10. The method of claim 1, wherein the second frequency is a relaxed frequency that is lower than a maximum operating frequency.

11. The method of claim 1, wherein the first operation is a write operation.

12. The method of claim 1, wherein the first operation is a read operation.

13. A data storage device, comprising:

a controller and a memory, wherein the controller includes a host interface and a memory interface,

the controller configured to perform a first operation on the memory through the memory interface at a first frequency of a timing circuit associated with the host interface to determine a first data pattern,

the controller further configured to perform a read operation on the memory through the memory interface at a second frequency of the timing circuit to determine a second data pattern; and

an interface timing adjustment engine configured to change the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

14. The data storage device of claim 13, further comprising a timing device, wherein the controller is further configured to adjust a frequency of a timing signal associated with the host interface using the timing device to obtain the first frequency and the second frequency.

15. The data storage device of claim 13, further comprising a plurality of latches coupled to the comparator and working in conjunction with the controller to determine whether the first pattern equals the second pattern.

16. The data storage device of claim 14, wherein the controller is further configured to generate a clock signal or a strobe signal, and wherein the timing signal includes the clock signal or the strobe signal.

17. The data storage device of claim 14, further comprising a memory device, wherein the memory device is configured to generate a read enable signal, and wherein the timing signal includes the read enable signal.

18. A data storage device, comprising:

means for perform a first operation on the memory through the memory interface at a first frequency associated with a host interface to determine a first data pattern;

means for performing a read operation on the memory through the memory interface at a second frequency to determine a second data pattern; and

means for changing the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

19. The data storage device of claim 18, further comprising a data bus coupled between the host interface and the memory interface, the data bus configured to communicatively couple a controller of a data storage device to a non-volatile memory of the data storage device.

20. The data storage device of claim 18, wherein the predetermined amount is based on a setup and hold time required by the read operation.

21. A method comprising:

in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,

(a) writing, by the controller, a write data pattern to the memory through the memory interface at a first frequency associated with the host;

(b) reading a read data pattern from the memory through the memory interface at a lower frequency having an associated risk of a setup/hold violation that is below a predetermined probability;

(c) comparing the write data pattern to the read data pattern;

(d) either;

responsive to the write data pattern being equal to the read data pattern according to the comparison, increasing the first frequency by a predetermined amount;

or

responsive to the write data pattern not being equal to the read data pattern according to the comparison, decreasing the first frequency by a predetermined amount; and

(e) repeating (a)-(c).

22. The method of claim 21, further comprising:

executing (a)-(c) responsive to the controller entering an idle mode.

23. The method of claim 21, further comprising:

waiting for an interrupt service routing to complete before executing (a)-(c).

24. A method comprising:

in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,

(a) reading, by the controller, a first read data pattern from the memory through the memory interface at a low frequency having an associated risk of a setup/hold violation that is below a predetermined probability;

(b) reading a second read data pattern from the memory through the memory interface at a second frequency higher than the low frequency associated with the host;

(c) comparing the first read data pattern to the second read data pattern;

(d) either;

responsive to the first read data pattern being equal to the second read data pattern according to the comparison, increasing the second frequency by a predetermined amount;

or

responsive to the first read data pattern not being equal to the second read data pattern according to the comparison, decreasing the second frequency by a predetermined amount; and

(e) repeating (a)-(c).

25. The method of claim 24, further comprising:

executing (a)-(c) responsive to the controller entering an idle mode.

26. The method of claim 24, further comprising:

waiting for an interrupt service routing to complete before executing (a)-(c).