NON-VOLATILE STORAGE WITH WEAR-ADJUSTED FAILURE PREDICTION

• US 20190056994A1
• Filed: 03/21/2018
• Published: 02/21/2019
• Est. Priority Date: 08/16/2017
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Shulkin, Arthur, Rozman, David, Eliash, Tomer
• Granted Patent: US 10,802,911 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells in a first time period and manage the set of non-volatile memory cells according to a probability of occurrence of a target FBC in a second time period that is subsequent to the first time period. The probability of occurrence of the target FBC during the second time period is calculated from a model of FBC distribution change of the set of non-volatile memory cells.

Claims

1. A non-volatile storage apparatus, comprising:

a set of non-volatile memory cells; and

one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells in a first time period and manage the set of non-volatile memory cells according to a probability of occurrence of a target FBC in a second time period that is subsequent to the first time period, the probability of occurrence of the target FBC during the second time period calculated from a model of FBC distribution change of the set of non-volatile memory cells.

2. The non-volatile storage apparatus of claim 1 further comprising Error Correction Code (ECC) circuits configured to generate the FBCs for the data read from the set of non-volatile memory cells in the first time period.

3. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is comprised of a plurality of blocks of non-volatile memory cells, a block of non-volatile memory cells forming a unit of erase, the one or more control circuits are configured to use the probability of occurrence of the target FBC for the second time period to determine an order for garbage collection of the plurality of blocks of non-volatile memory cells containing obsolete data.

4. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is comprised of a plurality of blocks of non-volatile memory cells, a block of non-volatile memory cells forming a unit of erase, the one or more control circuits are configured to use probabilities of occurrence of the target FBC for the second time period to identify a first block of non-volatile memory cells and a second block of non-volatile memory cells for a wear leveling operation to move data from the first block of non-volatile memory cells to the second block of non-volatile memory cells, the first block of non-volatile memory cells having a higher probability of occurrence of the target FBC in the second time period than the second block of non-volatile memory cells.

5. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is comprised of a plurality of blocks of non-volatile memory cells, a block of non-volatile memory cells forming a unit of erase, and the one or more control circuits are configured to adjust read threshold voltages of a block of non-volatile memory cells based on a high probability of occurrence of the target FBC in the second time period in the block of non-volatile memory cells.

6. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is comprised of a plurality of blocks of non-volatile memory cells, a block of non-volatile memory cells forming a unit of erase, the one or more control circuits are configured to use probabilities of occurrence of the target FBC for the second time period to identify one or more blocks of the plurality of blocks as having a high probability of becoming bad blocks during the second time period.

7. The non-volatile storage apparatus of claim 6 wherein the one or more control circuits are further configured to store user data in the one or more blocks when corresponding probabilities of occurrence of the target FBC are below a threshold and cease to store user data in the one or more blocks when corresponding probabilities of occurrence of the target FBC are above the threshold.

8. The non-volatile storage apparatus of claim 1 wherein the model of FBC distribution change of the set of non-volatile memory cells includes estimated changes in mean and standard deviation of the FBC distribution of the set of non-volatile memory cells between the first time period and the second time period.

9. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells form a non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate.

10. A method, comprising:

collecting failure bit counts (FBCs) of a first time period for data read from a set of non-volatile memory cells during the first time period;

obtaining one or more metrics of a distribution of the FBCs of the first time period;

calculating a probability of occurrence in a second time period of a target FBC, the second time period subsequent to the first time period, the probability of occurrence during the second time period calculated from the one or more metrics of the distribution of the FBCs of the first time period according to a model of FBC distribution change; and

operating the set of non-volatile memory cells according to the probability of occurrence in the second time period of the target FBC such that a subset of non-volatile memory cells of the set of non-volatile memory cells with a high probability of occurrence in the second time period of the target FBC is operated differently from other non-volatile memory cells of the set of non-volatile memory cells.

11. The method of claim 10 wherein operating the set of non-volatile memory cells according to the probability of occurrence in the second time period of the target FBC includes performing at least one of:

garbage collection, wear leveling, bad block identification, and read threshold voltage adjustment of the set of non-volatile memory cells according to the probability of occurrence in the second time period of the target FBC.

12. The method of claim 10 further comprising recording FBCs for a plurality of blocks of non-volatile memory cells of the set of non-volatile memory cells and calculating a probability of occurrence during the second time period of the target FBC for each block of the plurality of blocks of non-volatile memory cells.

13. The method of claim 10 wherein the first time period is an initialization period and the second time period is a period after substantial use of the set of non-volatile memory cells.

14. The method of claim 10 further comprising obtaining a mean and standard deviation of the distribution of FBCs of the first time period and calculating the probability of occurrence during the second time period of the target FBC by applying the model of FBC distribution change including mean and standard deviation change to obtain a distribution of FBCs of the second time period.

15. The method of claim 14 further comprising generating the model of FBC distribution change including mean and standard deviation change from modeling of at least one of:

data retention, program disturb, and read disturb effects.

16. The method of claim 14 wherein applying the model of FBC distribution change to obtain a distribution of FBCs of the second time period includes applying a mean offset to a mean FBC of the distribution of the FBCs of the first time period and applying a standard deviation offset to an FBC standard deviation of the first time period.

17. The method of claim 14 wherein applying the model of FBC distribution change to obtain a distribution of FBCs of the second time period includes calculating a predicted mean of the second time period from:

18. The method of claim 17 wherein applying the model of FBC distribution change to obtain the distribution of FBCs of the second time period further includes calculating a predicted standard deviation of the second time period from:

19. A system comprising:

a set of non-volatile memory cells;

means for obtaining failure bit counts (FBCs) for data read from the set of non-volatile memory cells in a first time period;

means for obtaining a mean and standard deviation of a cumulative distribution of the FBCs and generating one or more FBC probabilities for a subsequent second time period from mean and standard deviation of the cumulative distribution of the FBCs; and

means for modifying one or more operation directed to the set of non-volatile memory cells according to the one or more FBC probabilities.

20. The system of claim 19 further comprising means for performing at least one of:

garbage collection, wear leveling, and read threshold voltage adjustment, of the set of non-volatile memory cells according to the one or more FBC probabilities obtained from one or more indicators.

21. A system comprising:

a non-volatile memory die;

a controller coupled to the non-volatile memory die, the controller comprising;

Error Correction Code (ECC) circuits configured to generate Failure Bit Counts (FBCs) for data read from the non-volatile memory die; and

a statistical collection and analysis unit in communication with the ECC circuits, the statistical collection and analysis unit configured to collect the FBCs for the data read from the non-volatile memory die and to generate a plurality of block-specific predictions of FBC probabilities for a plurality of blocks of the non-volatile memory die at one or more subsequent time periods according collected FBCs and a model of FBC distribution change of the non-volatile memory die.