PIXEL CIRCUIT AND DISPLAY DEVICE HAVING THE SAME

• US 20190057648A1
• Filed: 06/08/2017
• Published: 02/21/2019
• Est. Priority Date: 03/07/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: XU, Yingsong
• Granted Patent: US 10,453,392 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A pixel circuit is disclosed that includes an organic light-emitting diode, a driving transistor connected in series with the organic light-emitting diode and having a gate connected to a first node and a drain connected to a second node, a dual-gate transistor coupled between the first node and the second node, and a leakage current suppression structure for suppressing a change in a driving current of the organic light-emitting diode caused by a leakage current flowing through the dual-gate transistor. A display device having the pixel circuit is also disclosed.

Claims

1. A pixel circuit comprising:

an organic light-emitting diode;

a driving transistor connected in series with the organic light-emitting diode and configured to drive the organic light-emitting diode to emit light by means of a driving current flowing through the organic light-emitting diode during a light emission phase, wherein the driving transistor has a gate connected to a first node and a drain connected to a second node;

a dual-gate transistor coupled between the first node and the second node to cause the driving transistor to form a diode structure when the dual-gate transistor is turned on, wherein the dual-gate transistor comprises two sub-transistors connected in series via a common terminal; and

a leakage current suppression structure for suppressing a change in the driving current caused by a leakage current flowing through the dual-gate transistor.

2. The pixel circuit of claim 1, wherein the leakage current suppression structure comprises at least one of a capacitor coupled between the first node and the common terminal or a Schottky diode coupled between the first node and the dual-gate transistor, wherein the Schottky diode is arranged to be reversely turned off to suppress flowing of the leakage current through the dual-gate transistor during the light emission phase.

3. The pixel circuit of claim 2, wherein the dual-gate transistor comprises:

an active layer;

an insulation layer arranged on the active layer;

a gate metal layer arranged on the insulation layer and comprising two gate metal regions spaced apart from and electrically connected to each other;

a first electrode in electrical contact with the active layer and connected to the first node; and

a second electrode in electrical contact with the active layer and connected to the second node.

4. The pixel circuit of claim 3, wherein the capacitor comprises a metal plate arranged such that the insulation layer is sandwiched between the metal plate and the active layer.

5. The pixel circuit of claim 4, wherein the metal plate is located in a different layer than the gate metal layer.

6. The pixel circuit of claim 4, wherein the metal plate is located in a same layer as the gate metal layer.

7. The pixel circuit of claim 3, wherein the first electrode is made of a metal, and wherein the Schottky diode comprises a hole blocking layer formed by metal-semiconductor contact between the first electrode and the active layer.

8. The pixel circuit of claim 7, wherein the active layer is made of polysilicon, and wherein the metal is selected from the group consisting of Ag, Au, Pt, and Al.

9. The pixel circuit of claim 1, wherein the two sub-transistors each have a gate connected to a first scan line, and wherein the pixel circuit further comprises:

a storage capacitor having a first terminal connected to the first node and a second terminal connected to a third node;

a third transistor connected between the driving transistor and the organic light-emitting diode and having a gate connected to a light emission control line;

a fourth transistor having a gate connected to a second scan line, a first electrode connected to an initialization voltage, and a second electrode connected to the first node;

a fifth transistor having a gate connected to the second scan line, a first electrode connected to a first power supply voltage, and a second electrode connected to the third node;

a sixth transistor having a gate connected to the first scan line, a first electrode connected to a data line, and a second electrode connected to the third node; and

a seventh transistor having a gate connected to the light emission control line, a first electrode connected to a reference voltage, and a second electrode connected to the third node.

10. The pixel circuit of claim 9, wherein the fourth transistor is configured to initialize a potential at the first node to the initialization voltage in response to a second scan signal from the second scan line, and wherein the fifth transistor is configured to initialize a potential at the third node to the first power supply voltage in response to the second scan signal.

11. The pixel circuit of claim 9, wherein the dual-gate transistor is configured to cause the driving transistor to form the diode structure in response to a first scan signal from the first scan line, and wherein the sixth transistor is configured to write a data voltage from the data line to the third node in response to the first scan signal.

12. The pixel circuit of claim 9, wherein the seventh transistor is configured to transfer the reference voltage to the third node in response to a light emission control signal from the light emission control line, and wherein the third transistor is configured to, responsive to the light emission control signal, provide a current path along which the drive current flows through the organic light-emitting diode.

13. A display device comprising:

a pixel array comprising a plurality of pixel circuits;

a first scan driver configured to supply scan signals to the pixel array;

a second scan driver configured to supply light emission control signals to the pixel array; and

a data driver configured to supply data signals to the pixel array,

wherein each of the plurality of pixel circuits comprises;

an organic light-emitting diode;

a driving transistor connected in series with the organic light-emitting diode and configured to drive the organic light-emitting diode to emit light by means of a driving current flowing through the organic light-emitting diode during a light emission phase, wherein the driving transistor has a gate connected to a first node and a drain connected to a second node;

a dual-gate transistor coupled between the first node and the second node to cause the driving transistor to form a diode structure when the dual-gate transistor is turned on, wherein the dual-gate transistor comprises two sub-transistors connected in series via a common terminal; and

a leakage current suppression structure for suppressing a change in the driving current caused by a leakage current flowing through the dual-gate transistor.

14. The display device of claim 13, wherein the leakage current suppression structure comprises at least one of a capacitor coupled between the first node and the common terminal or a Schottky diode coupled between the first node and the dual-gate transistor, wherein the Schottky diode is arranged to be reversely turned off to suppress flowing of the leakage current through the dual-gate transistor during the light emission phase.

15. The display device of claim 14, wherein the dual-gate transistor comprises:

an active layer;

an insulation layer arranged on the active layer;

a gate metal layer arranged on the insulation layer and comprising two gate metal regions spaced apart from and electrically connected to each other;

a first electrode in electrical contact with the active layer and connected to the first node; and

a second electrode in electrical contact with the active layer and connected to the second node.

16. The display device of claim 15, wherein the capacitor comprises a metal plate arranged such that the insulation layer is sandwiched between the metal plate and the active layer.

17. The display device of claim 16, wherein the metal plate is located on a different layer than the gate metal layer.

18. The display device of claim 16, wherein the metal plate is located in a same layer as the gate metal layer.

19. The display device of claim 15, wherein the first electrode is made of a metal, and wherein the Schottky diode comprises a hole blocking layer formed by metal-semiconductor contact between the first electrode and the active layer.

20. The display device of claim 19, wherein the active layer is made of polysilicon, and wherein the metal is selected from the group consisting of Ag, Au, Pt, and Al.