GOA CICUIT AND LCD DEVICE

• US 20190057663A1
• Filed: 10/24/2017
• Published: 02/21/2019
• Est. Priority Date: 08/15/2017
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Original Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Inventors: SHI, Longqiang
• Granted Patent: US 10,446,101 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Abstract

A GOA circuit includes a plurality of pull-up control units. An n-th stage pull-up control unit of top m-stage pull-up control units includes a signal-output-control circuit, a first switch unit, and a capacitor. The first switch unit includes a control terminal, a first terminal receiving an n-th stage clock signal, and a second terminal electrically connected with an nth-stage scanning line. The capacitor has a terminal electrically connected with the control terminal of the first switch unit and another terminal electrically connected with the second terminal of the first switch unit. The signal-output-control circuit charges the capacitor for a first time period and disconnects a discharging path of the capacitor for a second time period. The first time period and the second time period are consecutive time periods, and the second time period is subsequent to the first time period.

Claims

1. A gate driver on array (GOA) circuit, applied to a liquid crystal display (LCD) device, wherein the GOA circuit comprises a plurality of pull-up control units, an n-th stage pull-up control unit of top m-stage pull-up control units comprises a signal-output-control circuit, a first switch unit, and a capacitor, the first switch unit comprises a control terminal, a first terminal, and a second terminal, the control terminal of the first switch unit is electrically connected with one terminal of the capacitor, the first terminal of the first switch unit receives an n-th stage clock signal, and the second terminal of the first switch unit is electrically connected with an nth-stage scanning line, the terminal of the capacitor is electrically connected with the control terminal of the first switch unit, and another terminal of the capacitor is electrically connected with the second terminal of the first switch unit, the signal-output-control circuit charges the capacitor for a first time period and disconnects a discharging path of the capacitor for a second time period, wherein n is a positive integer M is a positive integer greater than or equal to n, the first time period and the second time period are consecutive time periods, and the second time period is subsequent to the first time period.

2. The GOA circuit according to claim 1, wherein the signal-output-control circuit comprises a second switch unit, a third switch unit and a fourth switch unit, during the first time period, the second switch unit is turned on, the third switch unit is turned off, the fourth switch unit is turned on, and the capacitor is charged;

during the second time period, the second switch unit is turned on, the third switch unit is turned on, the fourth switch unit is turned off, and the discharging path of the capacitor is disconnected.

3. The GOA circuit according to claim 2, wherein the second switch unit, the third switch unit, and the fourth switch unit all comprises a control terminal, a first terminal, and a second terminal, both the control terminal of the second switch unit and the first terminal of the second switch unit are loaded with a first signal, the second terminal of the second switch unit is electrically connected with the first terminal of the third switch unit, the control terminal of the third switch unit receives the n-th stage clock signal, the second terminal of the third switch unit is electrically connected with a first node to load a second signal, the control terminal of the fourth switch unit is electrically connected with the second terminal of the second switch unit, the first terminal of the fourth switch unit is electrically connected with the first terminal of the second switch unit, the second terminal of the fourth switch unit is electrically connected with the first node, and the second terminal of the fourth switch unit is electrically connected with the control terminal of the first switch unit;

during the first time period, the second switch unit is turned on, the third switch unit is turned off, the fourth switch unit is turned on, and the capacitor is charged;

during the second time period, the second switch unit is turned on, the third switch unit is turned on, the fourth switch unit is turned off, and the discharging path of the capacitor is disconnected.

4. The GOA circuit according to claim 3, wherein the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are all positive thin film transistors (PTFTs), the first signal is a low-level signal, the second signal is a high-level signal, the n-th stage clock signal is a high-level signal during the first time period, and the n-th stage clock signal is a low-level signal during the second time period.

5. The GOA circuit according to claim 3, wherein the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are all negative thin film transistors (NTFTs), the first signal is a high-level signal, the second signal is a low-level signal, the n-th stage clock signal is a low-level signal during the first time period, and the n-th stage clock signal is a high-level signal during the second time period.

6. The GOA circuit according to claim 5, wherein both the control terminal of the second switch unit and the first terminal of the second switch unit are connected with a second node, the second node receives a starting signal of the LCD device to load the first signal, the first node receives a low-level signal of the LCD device to load the second signal.

7. The GOA circuit according to claim 3, wherein the control terminal of the second switch unit is connected with a second node, the second node receives a starting signal of the LCD device to load the first signal, the first terminal of the second switch unit is connected with a direct current (DC) high-level power source to load the first signal, the first node receives a low-level signal of the LCD device to load the second signal.

8. The GOA circuit according to claim 1, wherein the signal-output-control circuit comprises a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, and a sixth switch unit;

the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit all comprises a control terminal, a first terminal, and a second terminal, both the control terminal of the second switch unit and the first terminal of the second switch unit are loaded with a first signal, the second terminal of the second switch unit is electrically connected with the first terminal of the third switch unit, the control terminal of the third switch unit receives the n-th stage clock signal, the second terminal of the third switch unit is electrically connected with a first node to load a second signal, the control terminal of the fourth switch unit is electrically connected with a second terminal of the second switch unit, the first terminal of the fourth switch unit receives the first signal, the second terminal of the fourth switch unit is electrically connected with the first terminal of the fifth switch unit, the control terminal of the fifth switch unit receives the n-th stage clock signal, the second terminal of the fifth switch unit is electrically connected with a first node to load the second signal, the control terminal of the sixth switch unit is electrically connected with the second terminal of the fourth switch unit, the first terminal of the sixth switch unit is electrically connected with the first terminal of the fourth switch unit, the second terminal of the sixth switch unit is electrically connected with the first node to load the second signal;

during the first time period, the second switch unit is turned on, the third switch unit is turned off, the fourth switch unit is turned on, the fifth switch unit is turned off, the sixth switch unit is turned on, and the capacitor is charged;

during the second time period, the second switch unit is turned on, the third switch unit is turned on, the fourth switch unit is turned off, and the discharging path of the capacitor is disconnected.

9. The GOA circuit according to claim 8, wherein the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are all positive thin film transistors (PTFTs), the first signal is a low-level signal, the second signal is a high-level signal, the n-th stage clock signal is a high-level signal during the first time period, and the n-th stage clock signal is a low-level signal during the second time period.

10. The GOA circuit according to claim 8, wherein the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are all negative thin film transistors (NTFTs), the first signal is a high-level signal, the second signal is a low-level signal, the n-th stage clock signal is a low-level signal during the first time period, and the n-th stage clock signal is a high-level signal during the second time period.

11. The GOA circuit according to claim 10, wherein the control terminal of the second switch unit, the first terminal of the second switch unit, and the first terminal of the fourth switch unit are all connected with a second node, the second node receives a starting signal of the LCD device to load the first signal, the second node receives a low-level signal of the LCD device to load the second signal.

12. The GOA circuit according to claim 10, wherein the control terminal of the second switch unit is connected with a second node, the second node receives a starting signal of the LCD device to load the first signal, the first terminal of the second switch unit and the first terminal of the fourth switch unit are both connected with a direct current (DC) high-level power source to load the first signal, the first node receives a low-level signal of the LCD device to load the second signal.

13. A liquid crystal display (LCD) device, comprising a gate driver on array (GOA) circuit, wherein the GOA circuit comprises a plurality of pull-up control units, an n-th stage pull-up control unit of top m-stage pull-up control units comprises a signal-output-control circuit, a first switch unit, and a capacitor, the first switch unit comprises a control terminal, a first terminal, and a second terminal, the control terminal of the first switch unit is electrically connected with one terminal of the capacitor, the first terminal of the first switch unit receives an n-th stage clock signal, and the second terminal of the first switch unit is electrically connected with an nth-stage scanning line, the terminal of the capacitor is electrically connected with the control terminal of the first switch unit, and another terminal of the capacitor is electrically connected with the second terminal of the first switch unit, the signal-output-control circuit charges the capacitor for a first time period and disconnects a discharging path of the capacitor for a second time period, wherein n is a positive integer M is a positive integer greater than or equal to n, the first time period and the second time period are consecutive time periods, and the second time period is subsequent to the first time period.

14. The LCD device according to claim 13, wherein the signal-output-control circuit comprises a second switch unit, a third switch unit and a fourth switch unit, during the first time period, the second switch unit is turned on, the third switch unit is turned off, the fourth switch unit is turned on, and the capacitor is charged;

during the second time period, the second switch unit is turned on, the third switch unit is turned on, the fourth switch unit is turned off, and the discharging path of the capacitor is disconnected.

15. The LCD device according to claim 14, wherein the second switch unit, the third switch unit, and the fourth switch unit all comprises a control terminal, a first terminal, and a second terminal, both the control terminal of the second switch unit and the first terminal of the second switch unit are loaded with a first signal, the second terminal of the second switch unit is electrically connected with the first terminal of the third switch unit, the control terminal of the third switch unit receives the n-th stage clock signal, the second terminal of the third switch unit is electrically connected with a first node to load a second signal, the control terminal of the fourth switch unit is electrically connected with the second terminal of the second switch unit, the first terminal of the fourth switch unit is electrically connected with the first terminal of the second switch unit, the second terminal of the fourth switch unit is electrically connected with the first node, and the second terminal of the fourth switch unit is electrically connected with the control terminal of the first switch unit;

during the first time period, the second switch unit is turned on, the third switch unit is turned off, the fourth switch unit is turned on, and the capacitor is charged;

during the second time period, the second switch unit is turned on, the third switch unit is turned on, the fourth switch unit is turned off, and the discharging path of the capacitor is disconnected.

16. The LCD device according to claim 15, wherein the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are all positive thin film transistors (PTFTs), the first signal is a low-level signal, the second signal is a high-level signal, the n-th stage clock signal is a high-level signal during the first time period, and the n-th stage clock signal is a low-level signal during the second time period.

17. The LCD device according to claim 15, wherein the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are all negative thin film transistors (NTFTs), the first signal is a high-level signal, the second signal is a low-level signal, the n-th stage clock signal is a low-level signal during the first time period, and the n-th stage clock signal is a high-level signal during the second time period.

18. The LCD device according to claim 17, wherein both the control terminal of the second switch unit and the first terminal of the second switch unit are connected with a second node, the second node receives a starting signal of the LCD device to load the first signal, the first node receives a low-level signal of the LCD device to load the second signal.

19. The LCD device according to claim 15, wherein the control terminal of the second switch unit is connected with a second node, the second node receives a starting signal of the LCD device to load the first signal, the first terminal of the second switch unit is connected with a direct current (DC) high-level power source to load the first signal, the first node receives a low-level signal of the LCD device to load the second signal.

20. The LCD device according to claim 13, wherein the signal-output-control circuit comprises a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, and a sixth switch unit;

the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit all comprises a control terminal, a first terminal, and a second terminal, both the control terminal of the second switch unit and the first terminal of the second switch unit are loaded with a first signal, the second terminal of the second switch unit is electrically connected with the first terminal of the third switch unit, the control terminal of the third switch unit receives the n-th stage clock signal, the second terminal of the third switch unit is electrically connected with a first node to load a second signal, the control terminal of the fourth switch unit is electrically connected with a second terminal of the second switch unit, the first terminal of the fourth switch unit receives the first signal, the second terminal of the fourth switch unit is electrically connected with the first terminal of the fifth switch unit, the control terminal of the fifth switch unit receives the n-th stage clock signal, the second terminal of the fifth switch unit is electrically connected with a first node to load the second signal, the control terminal of the sixth switch unit is electrically connected with the second terminal of the fourth switch unit, the first terminal of the sixth switch unit is electrically connected with the first terminal of the fourth switch unit, the second terminal of the sixth switch unit is electrically connected with the first node to load the second signal;

during the first time period, the second switch unit is turned on, the third switch unit is turned off, the fourth switch unit is turned on, the fifth switch unit is turned off, the sixth switch unit is turned on, and the capacitor is charged;

during the second time period, the second switch unit is turned on, the third switch unit is turned on, the fourth switch unit is turned off, and the discharging path of the capacitor is disconnected.

21-24. -24. (canceled)