GOA CICUIT AND LCD DEVICE

• US 20190057664A1
• Filed: 10/24/2017
• Published: 02/21/2019
• Est. Priority Date: 08/16/2017
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Original Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Inventors: SHI, Longqiang, CHEN, SHU JHIH
• Granted Patent: US 10,453,414 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A GOA driving circuit includes a plurality of cascaded GOA units and outputs a gate driving signal to an Nth-stage horizontal scanning line of a display region by an Nth-stage GOA unit. The Nth-stage GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down sustaining unit, a download unit, and a bootstrap capacitor unit. The pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor unit are respectively electrically connected with a first node and an Nth-stage horizontal scanning line. The pull-up control unit and the download unit are electrically connected with the first node. N is a positive integer. The Nth-stage GOA unit further includes a forced pull-down unit, which is used to force the first node to low level when clock signals are disappeared. A LCD device is also provided.

Claims

1. A gate driver on array (GOA) driving circuit, wherein the GOA driving circuit comprises a plurality of cascaded GOA units and outputs a gate driving signal to an Nth-stage horizontal scanning line of a display region by an Nth-stage GOA unit, the Nth-stage GOA unit comprises a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down sustaining unit, a download unit, and a bootstrap capacitor unit;

the pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor unit are respectively electrically connected with a first node and an Nth-stage horizontal scanning line, the pull-up control unit and the download unit are electrically connected with the first node, where N is a positive integer;

the Nth-stage GOA unit further comprises;

a forced pull-down unit for forcing the first node to low level when clock signals are disappeared.

2. The GOA driving circuit according to claim 1, wherein the forced pull-down unit comprises a twelfth thin film transistor (TFT), a gate electrode of the twelfth TFT is connected with a reset signal, a source electrode of the twelfth TFT is electrically connected with the first node, a drain electrode of the twelfth TFT is connected with a first low level, the reset signal changes from low level to high level when the clock signals are disappeared.

3. The GOA driving circuit according to claim 1, wherein the pull-down sustaining unit comprises a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, and an eleventh TFT;

a source electrode of the sixth TFT is connected with the first node, a drain electrode of the sixth TFT is connected with a first low level, a gate electrode of the sixth TFT is electrically connected with an Nth-stage second node;

a source electrode of the seventh TFT is electrically connected with the Nth-stage horizontal scanning line, and a drain electrode of the seventh TFT is connected with the first low level, a gate electrode of the seventh TFT is electrically connected with the Nth-stage second node;

a gate electrode and a source electrode of the eighth TFT are electrically connected with a first high level, and a drain electrode of the eighth TFT is electrically connected with a gate electrode of the ninth TFT and a source electrode of the eleventh TFT;

a source electrode of the ninth TFT is electrically connected with the first high level, a drain electrode of the ninth TFT is electrically connected with the Nth-stage second node;

a source electrode of the tenth TFT is electrically connected with the Nth-stage second node, a drain electrode of the ten TFT is connected with the first low level, and a gate electrode of the tenth TFT is electrically connected with the first node;

a drain electrode of the eleventh TFT is electrically connected with the first low level, a gate electrode of the eleventh TFT is electrically connected with the first node.

4. The GOA driving circuit according to claim 3, wherein the forced pull-down unit comprises a thirteenth TFT, a gate electrode of the thirteenth TFT is connected with a reset signal, a source electrode of the thirteenth TFT is electrically connected with the first high level, a drain electrode of the thirteenth TFT is electrically connected with an Nth-stage second node, the reset signal changes from low level to high level when the clock signals are disappeared.

5. The GOA driving circuit according to claim 3, wherein the clock signals comprise a first clock signal and a second clock signal, the first clock signal and the second clock signal have the same frequency, and in one cycle, phases of the first clock signal and the second clock signal except the blanking interval are opposite in phase;

the forced pull-down unit comprises an eighteenth TFT, a nineteenth TFT, a twentieth TFT, and a twenty-first TFT;

a source electrode and a gate electrode of the eighteenth TFT are electrically connected with the first high level, a drain electrode of the eighteenth TFT is electrically connected with a gate electrode of the nineteenth TFT, a source electrode of the twentieth TFT, and a source electrode of the twenty-first TFT respectively;

a source electrode of the nineteenth TFT is electrically connected with the first high level, a drain electrode of the nineteenth TFT is connected with the Nth-stage second node;

a gate electrode of the twentieth TFT is electrically connected with the first clock signal, a drain electrode of the twentieth TFT is electrically connected with the first low level;

a gate electrode of the twenty-first TFT is electrically connected with the second clock signal, and a drain electrode of the twenty-first TFT is electrically connected with the first low level.

6. The GOA driving circuit according to claim 1, wherein the clock signals comprise a first clock signal and a second clock signal, the first clock signal and the second clock signal have the same frequency, and in one cycle, phases of the first clock signal and the second clock signal except the blanking interval are opposite in phase;

the forced pull-down unit comprises an fourteenth TFT, a fifteenth TFT, a sixteenth TFT, and a seventeenth TFT;

a source electrode and a gate electrode of the fourteenth TFT are electrically connected with the first high level, a drain electrode of the fourteenth TFT is electrically connected with a gate electrode of the fifteenth TFT, a source electrode of the sixteenth TFT, and a source electrode of the seventeenth TFT respectively;

a source electrode of the fifteenth TFT is electrically connected with the first node, a drain electrode of the fifteenth TFT is connected with the first low level;

a gate electrode of the sixteenth TFT is electrically connected with the first clock signal, a drain electrode of the sixteenth TFT is electrically connected with the first low level;

a gate electrode of the seventeenth TFT is electrically connected with the second clock signal, and a drain electrode of the seventeenth TFT is electrically connected with the first low level.

7. The GOA driving circuit according to claim 1, wherein one cycle of the GOA driving circuit comprises a blanking interval, and the forced pull-down unit forces the first node to low level when the clock signals are disappeared except the blanking interval of the cycle of the GOA driving circuit.

8. The GOA driving circuit according to claim 2, wherein one cycle of the GOA driving circuit comprises a blanking interval, and the forced pull-down unit forces the first node to low level when the clock signals are disappeared except the blanking interval of the cycle of the GOA driving circuit.

9. The GOA driving circuit according to claim 3, wherein one cycle of the GOA driving circuit comprises a blanking interval, and the forced pull-down unit forces the first node to low level when the clock signals are disappeared except the blanking interval of the cycle of the GOA driving circuit.

10. The GOA driving circuit according to claim 4, wherein one cycle of the GOA driving circuit comprises a blanking interval, and the forced pull-down unit forces the first node to low level when the clock signals are disappeared except the blanking interval of the cycle of the GOA driving circuit.

11. The GOA driving circuit according to claim 5, wherein one cycle of the GOA driving circuit comprises a blanking interval, and the forced pull-down unit forces the first node to low level when the clock signals are disappeared except the blanking interval of the cycle of the GOA driving circuit.

12. The GOA driving circuit according to claim 6, wherein one cycle of the GOA driving circuit comprises a blanking interval, and the forced pull-down unit forces the first node to low level when the clock signals are disappeared except the blanking interval of the cycle of the GOA driving circuit.

13. The GOA driving circuit according to claim 1, wherein the pull-up unit comprises a third TFT, a source electrode of the third TFT is connected with a first clock signal, a gate electrode of the third TFT is electrically connected with the first node, and a drain electrode of the third TFT is electrically connected with the Nth-stage horizontal scanning line.

14. The GOA driving circuit according to claim 1, wherein the pull-down unit comprises a fourth TFT and a fifth TFT;

a source electrode of the fourth TFT is electrically connected with the first node, a drain electrode of the fourth TFT is connected with a first low level;

a source electrode of the fifth TFT is electrically connected with the Nth-stage horizontal scanning line, a drain electrode of the fifth TFT is connected with the first low level;

a gate electrode of the fourth TFT and a gate electrode of the fifth TFT are both connected with a (N+1)-stage download signal.

15. A liquid crystal display (LCD) device, which comprises a gate driver on array (GOA) driving circuit, wherein the GOA driving circuit comprises a plurality of cascaded GOA units and outputs a gate driving signal to an Nth-stage horizontal scanning line of a display region by an Nth-stage GOA unit, the Nth-stage GOA unit comprises a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down sustaining unit, a download unit, and a bootstrap capacitor unit;

the pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor unit are respectively electrically connected with a first node and an Nth-stage horizontal scanning line, the pull-up control unit and the download unit are electrically connected with the first node, where N is a positive integer;

the Nth-stage GOA unit further comprises;

a forced pull-down unit for forcing the first node to low level when clock signals are disappeared.

16. The LCD device according to claim 15, wherein the forced pull-down unit comprises a twelfth thin film transistor (TFT), a gate electrode of the twelfth TFT is connected with a reset signal, a source electrode of the twelfth TFT is electrically connected with the first node, a drain electrode of the twelfth TFT is connected with a first low level, the reset signal changes from low level to high level when the clock signals are disappeared.

17. The LCD device according to claim 15, wherein the pull-down sustaining unit comprises a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, and an eleventh TFT;

a source electrode of the sixth TFT is connected with the first node, a drain electrode of the sixth TFT is connected with a first low level, a gate electrode of the sixth TFT is electrically connected with an Nth-stage second node;

a source electrode of the seventh TFT is electrically connected with the Nth-stage horizontal scanning line, and a drain electrode of the seventh TFT is connected with the first low level, a gate electrode of the seventh TFT is electrically connected with the Nth-stage second node;

a gate electrode and a source electrode of the eighth TFT are electrically connected with a first high level, and a drain electrode of the eighth TFT is electrically connected with a gate electrode of the ninth TFT and a source electrode of the eleventh TFT;

a source electrode of the ninth TFT is electrically connected with the first high level, a drain electrode of the ninth TFT is electrically connected with the Nth-stage second node;

a source electrode of the tenth TFT is electrically connected with the Nth-stage second node, a drain electrode of the ten TFT is connected with the first low level, and a gate electrode of the tenth TFT is electrically connected with the first node;

a drain electrode of the eleventh TFT is electrically connected with the first low level, a gate electrode of the eleventh TFT is electrically connected with the first node.

18. The LCD device according to claim 17, wherein the forced pull-down unit comprises a thirteenth TFT, a gate electrode of the thirteenth TFT is connected with a reset signal, a source electrode of the thirteenth TFT is electrically connected with the first high level, a drain electrode of the thirteenth TFT is electrically connected with an Nth-stage second node, the reset signal changes from low level to high level when the clock signals are disappeared.

19. The LCD device according to claim 17, wherein the clock signals comprise a first clock signal and a second clock signal, the first clock signal and the second clock signal have the same frequency, and in one cycle, phases of the first clock signal and the second clock signal except the blanking interval are opposite in phase;

the forced pull-down unit comprises an eighteenth TFT, a nineteenth TFT, a twentieth TFT, and a twenty-first TFT;

a source electrode and a gate electrode of the eighteenth TFT are electrically connected with the first high level, a drain electrode of the eighteenth TFT is electrically connected with a gate electrode of the nineteenth TFT, a source electrode of the twentieth TFT, and a source electrode of the twenty-first TFT respectively;

a source electrode of the nineteenth TFT is electrically connected with the first high level, a drain electrode of the nineteenth TFT is connected with the Nth-stage second node;

a gate electrode of the twentieth TFT is electrically connected with the first clock signal, a drain electrode of the twentieth TFT is electrically connected with the first low level;

a gate electrode of the twenty-first TFT is electrically connected with the second clock signal, and a drain electrode of the twenty-first TFT is electrically connected with the first low level.

20. The LCD device according to claim 15, wherein the clock signals comprise a first clock signal and a second clock signal, the first clock signal and the second clock signal have the same frequency, and in one cycle, phases of the first clock signal and the second clock signal except the blanking interval are opposite in phase;

the forced pull-down unit comprises an fourteenth TFT, a fifteenth TFT, a sixteenth TFT, and a seventeenth TFT;

a source electrode and a gate electrode of the fourteenth TFT are electrically connected with the first high level, a drain electrode of the fourteenth TFT is electrically connected with a gate electrode of the fifteenth TFT, a source electrode of the sixteenth TFT, and a source electrode of the seventeenth TFT respectively;

a source electrode of the fifteenth TFT is electrically connected with the first node, a drain electrode of the fifteenth TFT is connected with the first low level;

a gate electrode of the sixteenth TFT is electrically connected with the first clock signal, a drain electrode of the sixteenth TFT is electrically connected with the first low level;

a gate electrode of the seventeenth TFT is electrically connected with the second clock signal, and a drain electrode of the seventeenth TFT is electrically connected with the first low level.