SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING SAME

• US 20190057930A1
• Filed: 11/10/2016
• Published: 02/21/2019
• Est. Priority Date: 03/16/2016
• Status: Active Grant

• Current Assignee: Haesung Ds Co., Ltd.
• Original Assignee: Haesung Ds Co., Ltd.
• Inventors: BAE, In Seob, KANG, Sung Il
• Granted Patent: US 10,643,932 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4828 Etching etching for cleaning without patterning H01L21/4835
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49586 Insulating layers on lead frames
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector

Abstract

A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.

Claims

1. A semiconductor package substrate in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, the semiconductor package substrate comprising:

a die pad formed of the conductive material on the upper surface; and

a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area,

wherein a protrusion protruding toward the lower surface is formed in a central area of the bonding pad, and a central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.

2. The semiconductor package substrate of claim 1, wherein the lead further comprises a connection pattern connected to the bonding pad, and the central thickness of the bonding pad is greater than a thickness of the connection pattern.

3. The semiconductor package substrate of claim 2, wherein a lower portion of the connection pattern and the bonding pad is filled with the resin.

4. The semiconductor package substrate of claim 1, wherein the lead further comprises a lead pad connected to the bonding pad, and a die land integrally formed with the die pad and a lead land integrally formed with the lead pad are provided on the lower surface.

5. The semiconductor package substrate of claim 1, wherein part of the resin between the die pad and the bonding pad is exposed, and the die pad, the bonding pad, and the exposed resin have the same height level.

6. The semiconductor package substrate of claim 1, further comprising:

a semiconductor chip mounted on the die pad; and

a wire boned to the semiconductor chip and the bonding pad.

7. A method of manufacturing a semiconductor package substrate, the method comprising:

forming a trench in a lower surface of a base substrate of a conductive material;

filling the trench with resin;

curing the resin;

removing the resin exposed from the trench; and

forming a die pad having a flat surface and a lead separated from the die pad on an upper surface of the base substrate, by patterning an opposite surface of the base substrate to expose at least a part of the resin filling the trench,

wherein the lead comprises a bonding pad having a flat surface and a connection pattern connected to the bonding pad,

at least a part of the trench is formed in an area corresponding to the lead, the trench has a first depth of an area corresponding to the bonding pad and a second depth of an area corresponding to the connection pattern, and the first depth is smaller than the second depth, and

the bonding pad that is an area where a wire is bonded comprises a protrusion protruding toward the lower surface, and the central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.

8. The method of claim 7, further comprising roughening an inner surface of the trench.

9. The method of claim 7, wherein the trench is formed by a half-tone mask process.

10. The method of claim 7, further comprising forming a plated layer on the lead.

11. A semiconductor package substrate in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, the semiconductor package substrate comprising:

a die pad formed of the conductive material on the upper surface;

a lead arranged on the upper surface by being electrically separated from the die pad, and comprising a bonding pad that is a wire bonding area, a connection pattern, and a lead pad; and

a lead land integrally formed with the lead pad on the lower surface,

wherein the bonding pad comprises a protrusion protruding toward the lower surface,

the connection pattern connects the bonding pad and the lead pad, and

a central thickness of the bonding pad is greater than a thickness of the connection pattern.

12. The semiconductor package substrate of claim 11, wherein the central thickness of the bonding pad has a value of about 50 μ

m to about 90 μ

m, and the thickness of the connection pattern has a value of about 10 μ

m to about 40 μ

m.

13. The semiconductor package substrate of claim 11, wherein a lower portion of the connection pattern and the bonding pad is filled with the resin.

14. The semiconductor package substrate of claim 11, wherein the protrusion is surrounded by the resin.

15. The semiconductor package substrate of claim 11, wherein the lead further comprises the lead pad connected to the bonding pad, and

a die land integrally formed with the die pad and a lead land integrally formed with the lead pad are provided on the lower surface.