SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20190057932A1
• Filed: 08/21/2017
• Published: 02/21/2019
• Est. Priority Date: 08/21/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WU, JIUN-YI, YU, CHEN-HUA, LIU, CHUNG-SHI, LEE, CHIEN HSUN
• Granted Patent: US 10,461,022 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/04 : characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/16 : Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/16153 : Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A semiconductor structure includes a first die including a first surface and a second surface opposite to the first surface; a molding surrounding the first die; a first via extended through the molding; an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer; and a second die disposed over the molding, wherein the second die is electrically connected to the first via.

Claims

1. A semiconductor structure, comprising:

a first die including a first surface and a second surface opposite to the first surface;

a molding surrounding the first die;

a via extended through the molding;

an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer;

a second die disposed over the molding and including a third surface facing the first die, a fourth surface opposite to the third surface and a sidewall between the third surface and the fourth surface;

a connector disposed between the second die and the via and being in contact with the third surface of the second die and the via; and

an underfill surrounding the connector and being in contact with a portion of the second surface of the first die,

wherein the second die is electrically connected to the via, and the underfill covers a portion of the sidewall of the second die and exposes entirely the fourth surface of the second die.

2. The semiconductor structure of claim 1, wherein the second die is at least partially overlapped with the first die.

3. The semiconductor structure of claim 1, wherein the second die is disposed over at least a portion of the second surface of the first die.

4. The semiconductor structure of claim 1, wherein the second die is electrically connected to the conductive member through the via.

5. The semiconductor structure of claim 1, wherein the second surface of the first die is exposed from the molding.

6. The semiconductor structure of claim 1, wherein the via is surrounded by the molding.

7. The semiconductor structure of claim 1, wherein the first die is disposed adjacent to the via.

8. The semiconductor structure of claim 1, further comprising a lid disposed over the second surface of the first die and configured to dissipate a heat from the first die.

9. The semiconductor structure of claim 8, wherein a portion of the lid is disposed over the second die.

10. A semiconductor structure, comprising:

a first die including a first surface and a second surface opposite to the first surface;

a molding surrounding the first die;

a via extended through the molding;

an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer;

a second die disposed over the molding and the via and including a third surface facing the first die, a fourth surface opposite to the third surface and a sidewall between the third surface and the fourth surface;

a first underfill disposed between the molding and the second die, and covering a portion of the sidewall of the second die and exposing entirely the fourth surface of the second die;

a substrate including a fifth surface facing the interconnect structure and a sixth surface opposite to the fifth surface;

a first conductive bump disposed between the interconnect structure and the fifth surface of the substrate; and

a second conductive bump disposed over the sixth surface of the substrate, wherein the second die is disposed over at least a portion of the second surface of the first die.

11. The semiconductor structure of claim 10, wherein the first die is electrically connected to the second die through the via and the conductive member.

12. The semiconductor structure of claim 10, wherein the second die is electrically isolated from the via or the conductive member.

13. The semiconductor structure of claim 10, wherein the first die is a logic die, and the second die is a high bandwidth memory (HBM) die.

14. The semiconductor structure of claim 10, further comprising a second underfill disposed over the fifth surface of the substrate and surrounding the first conductive bump.

15. The semiconductor structure of claim 14, wherein the second underfill is in contact with a sidewall of the dielectric layer.

17. The semiconductor structure of claim 10, wherein the first underfill is in contact with at least a portion of the second surface of the first die.

16. (canceled)

18. A method of manufacturing a semiconductor structure, comprising:

forming an interconnect structure including a dielectric layer and a conductive member disposed within the dielectric layer;

forming a via over the interconnect structure after the forming of the interconnect structure;

disposing a first die over the interconnect structure;

forming a molding over the interconnect structure and around the first die and the via; and

disposing a second die over the molding,

wherein a connector is disposed between the second die and the via and in contact with the via, and the second die is electrically connected to the via through the connector.

19. The method of claim 18, wherein the second die is disposed over at least a portion of the first die.

20. The method of claim 18, further comprising:

providing a substrate;

disposing a first conductive bump between the interconnect structure and the substrate;

disposing a first underfill between the interconnect structure and the substrate and around the first conductive bump; and

disposing a second underfill between the molding and the second die.

21. The method of claim 20, further comprising disposing a lid over the substrate.