CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

• US 20190057972A1
• Filed: 10/23/2018
• Published: 02/21/2019
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Ming Chyi, Liu, Shih-Chang, Chen, Sheng-Chieh, Chang, Yu-Hsing
• Granted Patent: US 10,461,089 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region

Abstract

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Claims

1. An integrated circuit (IC) comprising:

a semiconductor substrate including a peripheral region and a memory region separated by an isolation structure, wherein the isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material;

a memory cell on the memory region;

a dummy control gate structure on the isolation structure, wherein the dummy control gate structure defines a dummy sidewall that faces the peripheral region and that comprises multiple different materials;

a sidewall spacer on the isolation structure, along the dummy sidewall of the dummy control gate structure, wherein the sidewall spacer has a boundary sidewall that faces the peripheral region and that is smooth; and

a logic device on the peripheral region.

2. The IC according to claim 1, wherein the boundary sidewall is continuous and smooth from a topmost surface of the sidewall spacer to a bottommost surface of the sidewall spacer.

3. The IC according to claim 1, wherein the boundary sidewall is slanted downward towards the peripheral region.

4. The IC according to claim 1, wherein the boundary sidewall is at an angle of less than about 80 degrees relative to a bottommost surface of the sidewall spacer.

5. The IC according to claim 1, wherein the dummy sidewall is heterogenous, and wherein the boundary sidewall is homogeneous.

6. The IC according to claim 1, wherein the dummy control structure comprises an oxide-nitride-oxide (ONO) film, and further comprises a dummy gate electrode overlying the ONO film, and wherein the dummy sidewall is smooth and defined at least in part by the ONO film and the dummy gate electrode.

7. The IC according to claim 1, wherein the dummy sidewall is vertical or substantially vertical, wherein the sidewall spacer directly contacts the dummy sidewall, and wherein the dummy sidewall and the boundary sidewall are on opposite sides of the sidewall spacer.

8. The IC according to claim 1, wherein the memory cell comprises:

a first individual source/drain region and a second individual source/drain region both in the semiconductor substrate;

a common source/drain region in the semiconductor substrate, laterally spaced between the first and second individual source/drain regions, wherein the common source/drain region is separated from the first individual source/drain region by a first channel region, and wherein the common source/drain region is separated from the second individual source/drain region by a second channel region;

an erase gate electrode on the common source/drain region;

a pair of floating gate electrodes respectively on the first and second channel regions;

a pair of control gate electrodes respectively overlying the floating gate electrodes; and

a pair of select gate electrodes respectively on the first and second channel regions, and laterally spaced from the common source/drain respectively by the floating gate electrodes.

9. The IC according to claim 1, wherein the logic device comprises:

a high κ

gate dielectric layer; and

a metal gate electrode overlying the high κ

dielectric layer.

10. An integrated circuit (IC) comprising:

a semiconductor substrate;

an isolation structure extending into a top of the semiconductor substrate and comprising dielectric material;

a memory cell on the semiconductor substrate, wherein the memory cell comprises a control gate electrode and a control gate dielectric layer, and wherein the control gate electrode overlies the control gate dielectric layer;

a dummy structure on the isolation structure and comprising a dummy gate electrode and a dummy gate dielectric layer, wherein the dummy gate electrode and the dummy gate dielectric layer are respectively even with the control gate electrode and the control gate dielectric layer, and wherein the dummy gate electrode and the dummy gate dielectric layer collectively define a dummy sidewall; and

a sidewall spacer overlying the isolation structure and covering the dummy sidewall from a bottom of the dummy gate dielectric layer to a top of the dummy gate electrode, wherein the sidewall spacer has an angled sidewall on an opposite side of the sidewall spacer as the dummy structure.

11. The IC according to claim 10, wherein the isolation structure has an angled sidewall that is continuous with the angled sidewall of the sidewall spacer.

12. The IC according to claim 10, wherein the dummy gate electrode and the dummy gate dielectric layer contact at a first interface, and wherein the control gate electrode and the control gate dielectric layer contact at a second interface that is even with the first interface.

13. The IC according to claim 10, wherein the dummy gate electrode and the control gate electrode have the same composition, and wherein the dummy gate dielectric layer and the control gate dielectric layer have the same composition.

14. The IC according to claim 10, wherein dummy gate electrode and the sidewall spacer comprise the same material.

15. An integrated circuit (IC) comprising:

a semiconductor substrate;

an isolation structure extending into a top of the semiconductor substrate and comprising dielectric material;

a logic device adjacent to the isolation structure and comprising a gate dielectric layer and a gate electrode, wherein the gate electrode overlies the gate dielectric layer;

a multilayer stack on the isolation structure, wherein the multilayer stack has a heterogeneous sidewall that faces the logic device and that comprises multiple different materials; and

a sidewall spacer on the isolation structure, wherein the sidewall spacer is even with the gate electrode and has a bottom surface elevated above a bottom surface of the gate dielectric layer, and wherein the sidewall spacer contacts the heterogeneous sidewall from top to bottom and is a single material.

16. The IC according to claim 15, wherein a width of the sidewall spacer increases from top to bottom.

17. The IC according to claim 15, wherein a cross-sectional profile of the sidewall spacer is right-trapezoid shaped.

18. The IC according to claim 15, wherein the bottom surface of the sidewall spacer is elevated above a top surface of the gate dielectric layer.

19. The IC according to claim 15, wherein the sidewall spacer has a top surface that is even with a top surface of the gate electrode.

20. The IC according to claim 15, further comprising:

a dummy structure on the isolation structure, laterally spaced from and between the sidewall spacer and the logic device, wherein the dummy structure comprises a dummy gate electrode and a dummy gate dielectric layer.