AUTOMATIC DETECTION OF CHANGE IN PLL LOCKING TREND

• US 20190058575A1
• Filed: 08/21/2018
• Published: 02/21/2019
• Est. Priority Date: 04/21/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Tsung-Hsien, Chang, Chih-Hsien
• Granted Patent: US 10,439,794 B2
• Time in Patent Office: Days
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0994 comprising an accumulator
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Claims

1. A phase lock loop (PLL) controller, comprising:

a trend detector configured to;

sample an error signal, the error signal representing a difference between a reference input signal of the PLL and an output signal of the PLL, and

determine a trend of the sampled error signal; and

a trend change detector configured to initiate a change in a mode of operation of the PLL upon detecting a. change in the trend of the sampled error signal from a previous trend of the sampled error signal.

2. The PLL controller of claim 1, wherein the trend comprises:

a positive trend;

a negative trend;

or

a flat trend.

3. The PLL controller of claim 1, further comprising:

a clock generator configured to determine a trend clocking signal based upon the reference input signal and the error signal,

wherein the trend detector is configured to sample the error signal in accordance with the trend clocking signal.

4. The PLL controller of claim 3, wherein the clock generator is further configured to:

provide the trend clocking signal at a first logical value when the error signal is at a first digital value,

hold the trend clocking signal at the first logical level until the error signal changes to a second digital value, and

switch the trend clocking signal from the first logical level to the second logical level in response to the error signal changing to the second digital value.

5. The PLL controller of claim 1, wherein the PLL is further configured to adjust a frequency of the output signal to be proportional to a frequency of the reference input signal in a frequency tracking mode of operation,

wherein the PLL is further configured to adjust a phase of the output signal to match a phase of the reference input signal in a phase tracking mode of operation, and

wherein the trend change detector is further configured to switch a mode of operation of the PLL among the frequency tracking mode of operation and the phase tracking mode of operation upon detecting the change in the trend of the sampled error signal.

6. The PLL controller of claim 5, further comprising:

a phase frequency detector (PFD) configured to compare a frequency of the reference input signal and a frequency of the output signal to provide a frequency difference of the error signal in the frequency tracking mode of operation and in the phase tracking mode of operation.

7. The PLL controller of claim 6, further comprising:

a time-to-digital converter (TDC) configured to;

compare a phase of the reference input signal and a phase of the output signal to provide a phase difference of the error signal in the phase tracking mode of operation, and

be disabled in the frequency tracking mode of operation.

13. The method of claim 2, wherein the adjusting the frequency of the output signal comprises:

comparing a frequency of the reference input signal and a frequency of the output signal to provide a frequency difference of the error signal in the frequency tracking mode of operation and in the phase tracking mode of operation.

14. The method of claim 13, wherein the adjusting the phase of the output signal comprises:

comparing a phase of the reference input signal and a phase of the output signal to provide a phase difference of the error signal in the phase tracking mode of operation.

8. A method for operating a phase lock loop (PLL), the method comprising:

sampling an error signal from the PLL received in a frequency tracking mode of operation, the error signal representing a difference between a frequency of a reference input signal of the PLL and a frequency of an output signal of the PLL;

determining a trend of the sampled error signal;

initiating a change in a mode of operation of the PLL from the frequency tracking mode of operation to a phase tracking mode of operation upon detecting a change in the trend of the sampled error signal from a previous trend of the sampled error signal.

9. The method of claim 8, wherein the trend comprises:

a positive trend;

a negative trend;

or

a flat trend.

10. The method of claim 8, further comprising:

determining a trend clocking signal based upon the reference input signal and the error signal, and

wherein the sampling comprises;

sampling the error signal in accordance with the trend clocking signal.

11. The method of claim 10, wherein the determining the trend clocking signal comprises:

providing the trend clocking signal at a first logical value when the error signal is at a first digital value,

holding the trend clocking signal at the first logical level until the error signal changes to a second digital value, and

switching the trend clocking signal from the first logical level to the second logical level in response to the error signal changing to the second digital value.

12. The method of claim 8, further comprising:

adjusting a frequency of the output signal to be proportional to a frequency of the reference input signal in a frequency tracking mode of operation;

adjusting a phase of the output signal to match a phase of the reference input signal in the phase tracking mode of operation; and

switching a mode of operation of the PLL among the frequency tracking mode of operation and the phase tracking mode of operation upon detecting the change in the trend of the sampled error signal.

15. A controller for controlling a phase lock loop (PLL), the controller comprising:

means for sampling an error signal, the error signal representing a difference between a reference input signal of the PLL and an output signal of the PLL;

means for determining a trend of the sampled error signal; and

means for initiating a change in a mode of operation of the PLL upon detecting a change in the trend of the sampled error signal from a previous trend of the sampled error signal,

16. The PLL controller of claim 15, wherein the trend comprises:

means for determining a trend clocking signal based upon the reference input signal and the error signal,

wherein the means for sampling is configured to sample the error signal in accordance with the trend clocking signal.

17. The PLL controller of claim 16, wherein the means for determining the trend clocking signal is further configured to:

provide the trend clocking signal at a first logical value when the error signal is at a first digital value,

hold the trend clocking signal at the first logical level until error signal changes to a second digital value, and

switch the trend clocking signal from the first logical level to the second logical level in response to the error signal changing to the second digital value.

18. The PLL controller of claim 15, wherein the PLL is further configured to adjust a frequency of the output signal to be proportional to a frequency of the reference input signal in a frequency tracking mode of operation,

wherein the PLL is further configured to adjust a phase of the output signal to match a phase of the reference input signal in a phase tracking mode of operation, and

wherein the trend change detector is further configured to switch a mode of operation of the PLL among the frequency tracking mode of operation and the phase tracking mode of operation upon detecting the change in the trend of the sampled error signal.

19. The PLL controller of claim 18, further comprising:

means to compare a frequency of the reference input signal and a frequency of the output signal to provide a frequency difference of the error signal in the frequency tracking mode of operation and in the phase tracking mode of operation.

20. The PLL controller of claim 19, further comprising:

means to compare a phase of the reference input signal and a phase of the output signal to provide a phase difference of the error signal in the phase tracking mode of operation.