SMOOTH WAGEGUIDE STRUCTURES AND MANFACTURING METHODS

• US 20190064439A1
• Filed: 08/29/2017
• Published: 02/28/2019
• Est. Priority Date: 08/29/2017
• Status: Active Grant

• Current Assignee: Openlight Photonics Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Feshali, Avi, Hutchinson, John, Bauters, Jared
• Granted Patent: US 10,641,957 B2
• Time in Patent Office: Days
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12097 Ridge, rib or the like
• CPC Class Codes: G02B 6/12002 Three-dimensional structures
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: G02B 6/1228 Tapered waveguides, e.g. integrated spot-size transformers for coupling with fibres G02B6/305
• CPC Class Codes: G02B 6/132 by deposition of thin films
• CPC Class Codes: G02B 6/136 by etching

Abstract

In integrated optical structures (e.g., silicon-to-silicon-nitride mode converters) implemented in semiconductor-on-insulator substrates, wire waveguides whose sidewalls substantially consist of portions coinciding with crystallographic planes and do not extend laterally beyond the top surface of the wire waveguide may provide benefits in performance and/or manufacturing needs. Such wire waveguides may be manufactured, e.g., using a dry-etch of the semiconductor device layer down to the insulator layer to form a wire waveguide with exposed sidewalls, followed by a smoothing crystallographic wet etch.

Claims

1. An integrated optical structure comprising:

a semiconductor-on-insulator substrate comprising a semiconductor device layer; and

a wire waveguide formed in the semiconductor device layer, the wire waveguide having a top surface and sidewalls, wherein the sidewalls, along at least a portion of a length of the wire waveguide, do not extend laterally beyond the top surface of the wire waveguide and substantially consist of sidewall portions coinciding with crystallographic planes of the wire waveguide.

2. The integrated optical structure of claim 1, wherein the sidewall portions comprise, along at least the portion of the length of the wire waveguide, one or more substantially planar upper portions extending from a top edge of the wire waveguide at an acute angle with respect to the top surface of the wire waveguide and one or more substantially planar lower portions extending from a bottom edge of the wire waveguide at an acute angle with respect to a bottom surface of the wire waveguide, the upper and lower portions meeting at a medial horizontal plane of the wire waveguide.

3. The integrated optical structure of claim 1, wherein the sidewalls have sub-nanometer surface roughness.

4. The integrated optical structure of claim 1, wherein the substrate is a silicon-on-insulator substrate.

5. The integrated optical structure of claim 1, wherein the wire waveguide is tapered in width.

6. The integrated optical structure of claim 5, further comprising a rib waveguide formed in the semiconductor device layer on top of and parallel to the wire waveguide, the rib waveguide being tapered in at least one of width and height in a same direction along a length of the rib waveguide as the wire waveguide.

7. The integrated optical structure of claim 5, further comprising, disposed above or below the tapered wire waveguide, at least at a narrow end thereof, a second waveguide made from a different material than the wire waveguide, the wire waveguide and the second waveguide together forming a waveguide mode converter.

8. The integrated optical structure of claim 7, wherein a refractive index of a material of the wire waveguide is greater than a refractive index of the material of the second waveguide.

9. The integrated optical structure of claim 8, wherein the wire waveguide is made of silicon and the second waveguide is made of silicon nitride.

10. The integrated optical structure of claim 1, wherein, along a portion of the wire waveguide that has a width of less than 0.5 μ

m, a return loss is less than −

40 dB/mm across an operating wavelength range.

11. A photonic integrated circuit (PIC) comprising:

an optical mode converter comprising a first waveguide made of a first material and tapered towards one end, and, disposed above or below the first waveguide at the tapered end, a second waveguide made of a second material, a refractive index of the first material being greater than a refractive index of the second material,

wherein the first waveguide is a wire waveguide having a top surface and sidewalls, and wherein the sidewalls, along at least a portion of a length of the wire waveguide, do not extend laterally beyond the top surface and substantially consist of sidewall portions coinciding with crystallographic planes of the wire waveguide.

12. The PIC of claim 11, wherein the wire waveguide is formed in a silicon device layer of a silicon-on-insulator substrate and the second waveguide is formed in a silicon-nitride layer disposed above the silicon device layer, the PIC further comprising a silicon-nitride grating coupler coupled to the second waveguide and one or more silicon devices coupled to the wire waveguide.

13. A method of manufacturing an integrated optical structure, the method comprising:

creating a wire-waveguide etch mask above a semiconductor device layer of a semiconductor-on-insulator substrate;

dry-etching the masked semiconductor device layer down to an insulator layer of the substrate to form a semiconductor wire waveguide with exposed sidewalls;

crystallographically wet-etching the semiconductor wire waveguide to smoothen the exposed sidewalls, the etch being pinned between the insulator layer of the substrate and the wire-waveguide mask.

14. The method of claim 13, wherein an anisotropic etchant with an etch-rate ratio of at least 20 is used for the crystallographic wet-etching.

15. The method of claim 14, wherein the etchant comprises tetramethyl ammonium hydroxide.

16. The method of claim 13, further comprising, prior to creating the wire-waveguide etch mask, creating a rib-waveguide etch mask above the semiconductor device layer and partially etching the semiconductor device layer to form a semiconductor rib waveguide, wherein the semiconductor wire waveguide is formed, at least in part, running underneath the rib waveguide.

17. The method of claim 13, wherein the rib-waveguide etch mask and the wire-waveguide etch mask are both tapered so as to result in tapering of the semiconductor rib waveguide and the semiconductor wire waveguide in a common direction.

18. The method of claim 17, wherein the semiconductor rib waveguide is tapered vertically down to vanishing.

19. The method of claim 13, wherein the semiconductor device layer and the semiconductor wire waveguide are made of silicon.

20. The method of claim 19, further comprising creating a silicon-nitride waveguide above the silicon wire waveguide by depositing a silicon nitride layer above the top silicon layer, and patterning and etching the silicon nitride layer.