SLC CACHE MANAGEMENT
First Claim
1. A memory device, the memory device comprising:
- an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration;
a controller, the controller executing firmware instructions, which cause the controller to perform operations comprising;
receiving over a communications interface, a behavior profile for an SLC cache of the memory device, the behavior profile describing an SLC cache allocation;
configuring memory cells of the array as belonging either to an SLC cache pool or an MLC storage pool based upon the behavior profile;
receiving a write command to write data to the memory device;
writing the data to the SLC cache pool; and
subsequent to writing the data to the SLC cache pool, transferring the data to the MLC storage pool.
7 Assignments
0 Petitions
Accused Products
Abstract
Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.
31 Citations
21 Claims
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1. A memory device, the memory device comprising:
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an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration; a controller, the controller executing firmware instructions, which cause the controller to perform operations comprising; receiving over a communications interface, a behavior profile for an SLC cache of the memory device, the behavior profile describing an SLC cache allocation; configuring memory cells of the array as belonging either to an SLC cache pool or an MLC storage pool based upon the behavior profile; receiving a write command to write data to the memory device; writing the data to the SLC cache pool; and subsequent to writing the data to the SLC cache pool, transferring the data to the MLC storage pool. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
at a memory device comprising an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, using a controller, performing operations comprising; receiving over a communications interface, a behavior profile for an SLC cache of the memory device, the behavior profile describing an SLC cache allocation; configuring memory cells of the array as belonging either to an SLC cache pool or an MLC storage pool based upon the behavior profile; receiving a write command to write data to the memory device; writing the data to the SLC cache pool; and subsequent to writing the data to the SLC cache pool, transferring the data to the MLC storage pool. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A machine-readable medium comprising instructions, that when executed by a machine, cause the machine to perform operations comprising:
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receiving over a communications interface, a behavior profile for an SLC cache of a memory device, the behavior profile describing an SLC cache allocation; configuring memory cells of an array of memory cells as belonging either to an SLC cache pool or an MLC storage pool based upon the behavior profile; receiving a write command to write data to the memory device; writing the data to the SLC cache pool; and subsequent to writing the data to the SLC cache pool, transferring the data to the MLC storage pool. - View Dependent Claims (18, 19, 20, 21)
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Specification