CREDIT BASED COMMAND SCHEDULING

• US 20190065086A1
• Filed: 08/23/2017
• Published: 02/28/2019
• Est. Priority Date: 08/23/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Margetts, Julien, Jeong, Hyoun Kwon, Kim, Jonghyeon
• Granted Patent: US 11,029,859 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.

Claims

1. A memory system comprising:

a memory controller having;

a bank command scheduler implemented in a hardware logic block, and

a power budget controller including a budget register and a credit register;

a memory bank having an I/O bus; and

a channel connecting the I/O bus to the memory controller, the channel configured to transmit data between the memory bank and the memory controller and to transmit a command from the memory controller to the memory bank,

wherein the hardware logic block is configured to;

determine a first command in a queue to be transmitted to the memory bank;

estimate a first power consumption value for the first command;

query the power budget controller to determine if the first power consumption value satisfies a threshold; and

if the first power consumption value satisfies the threshold;

transmit the first command to the memory bank over the channel; and

transmit a signal to the power budget controller indicating that the first command has been executed.

2. The memory system of claim 1, wherein by querying the power budget controller to determine if the first power consumption value satisfies a threshold comprises comparing the first power consumption value to a difference between the credit register and the budget register.

3. The memory system of claim 1, wherein if the first power consumption value does not satisfy the threshold, the hardware logic block is configured to:

determine a second command in the queue to be transmitted to the memory bank;

estimate a second power consumption value for the second command; and

query the power budget controller to determine if the second power consumption value satisfies the threshold.

4. The memory system of claim 1, wherein if the first power consumption value does not satisfy the threshold, the hardware logic block is configured to wait until the first power consumption value satisfies the threshold.

5. The memory system of claim 4, wherein the power budget controller is configured to:

begin a timer associated with an idle time; and

when the timed idle time exceeds an idle time threshold, give the first command is priority over other commands.

6. The memory system of claim 1, wherein the first command comprises a first phase and a second phase, and wherein the hardware logic block is configured to:

estimate a third power consumption value for the first phase;

query the power budget controller to determine if the third power consumption value for the first phase satisfies the threshold; and

transmit the first phase to the memory bank over the channel.

7. The memory system of claim 4, wherein the first command is a read command, the first phase is a cell sensing phase, and the second phase is an I/O switching phase.

8. The memory system of claim 4, wherein the first command is a program command, the first phase is an I/O switching phase, and the second phase is a cell program phase.

9. The memory system of claim 1, wherein the hardware logic is configured to estimate a first power consumption value for the first command by accessing a register of estimated power consumption values for a given command.

10. The memory system of claim 1, wherein the hardware logic is further configured to:

monitor an actual power over an I/O power rail and a cell power rail; and

transmit, to the power budget controller, a measured actual power over the I/O power rail and the cell power rail.

11. The memory system of claim 1, wherein the a power budget controller is configured to:

receive, from the hardware logic block, a first power consumption value;

compare the first power consumption value to a difference between the values stored in the power budget register and the credit register;

add the first power consumption value to the credit register;

transmit a grant response if the first power consumption value is less than the difference;

receive a status from the hardware logic block indicating that the first command has been executed; and

remove the first power consumption value from the credit register.

12. The memory system of claim 11, wherein the power budget controller is further configured to determine if there is a priority command before adding the first power consumption value to the credit register and transmitting the grant response.

13. The memory system of claim 11, wherein the power budget controller is further configured to

determine if a first phase of the first command can be transmitted in parallel with a previously transmitted command and have a combined power consumption value that satisfies a threshold;

and

provide timing instructions to the hardware logic for interleaving a first phase of the first command with the preceding command being executed.

15. The method of claim 13, the method further comprising:

selecting the second phase of the first command;

estimating a second power consumption value of the second phase;

comparing, at a power budget controller, the estimated second power consumption value to a difference between a current value of the power credit register and the value of the power budget register;

if the estimated second power consumption value is less than the difference;

adding the estimated second power consumption value to the current value of the power credit register;

transmitting the second phase of the first command to the NAND bank over the channel; and

subtracting, after the second phase of the first command has executed, the estimated second power consumption value from the current value of the power credit register.

16. The method of claim 13, the method further comprising:

selecting the second phase of the first command;

estimating a second power consumption value of the second phase;

comparing, at a power budget controller, the estimated second power consumption value to a difference between a current value of the power credit register and the value of the power budget register;

if the estimated second power consumption value is greater than the difference;

beginning a wait counter for the second phase of the first command; and

labeling the second phase of the first command as a priority command.

17. The method of claim 15, the method further comprising:

waiting until the estimated second power consumption value is greater than a newly compared difference between the values stored in the power credit register and the power budget register; and

adding the estimated second power consumption value to the present power credit register;

transmitting the second phase of the first command to the NAND bank over the channel; and

subtracting, after the second phase of the first command has executed, the estimated second power consumption value from the value stored in the power credit register.

18. The method of claim 13, wherein estimating a first power consumption value of the first phase comprises determining an estimated power consumption of an I/O switching command.

19. The method of claim 13, wherein estimating a first power consumption value of the first phase comprises determining an estimated power consumption of a cell sensing command.

20. The method of claim 13, the method further comprising:

selecting, by a hardware logic block after transmitting the first command, a second command to send to a NAND bank over a channel;

determining that the second command does not have more than one phase;

estimating a third power consumption value of the second command; and

comparing, at a power budget controller, the estimated third power consumption value to a difference between the current value of the power credit register including the added first power consumption value and the value of the power budget register.

14. A method of transmitting commands based on a power consumption budget, the method comprising:

selecting, by a hardware logic block, a first command to send to a NAND bank over a channel;

selecting a first phase of the first command;

estimating a first power consumption value of the first phase;

comparing, at a power budget controller, the estimated first power consumption value to a difference between a value of a present power credit register and a value of a power budget register;

if the estimated first power consumption value is less than the difference;

adding the estimated first power consumption value to the value of the present power credit register;

transmitting the first phase of the first command to the NAND bank over the channel; and

subtracting, after the first phase of the first command has executed, the estimated first power consumption value from the value of the present power credit register.