PROVIDING EFFICIENT MULTIPLICATION OF SPARSE MATRICES IN MATRIX-PROCESSOR-BASED DEVICES
First Claim
1. A matrix-processor-based device comprising a matrix processor, wherein:
- the matrix processor comprises a plurality of sequencers communicatively coupled to one or more multiply/accumulate (MAC) units of a plurality of MAC units; and
the matrix processor is configured to;
receive a first input matrix and a second input matrix;
select, by each sequencer of the plurality of sequencers, an element of the first input matrix and an element of the second input matrix to be multiplied;
determine, by the sequencer, whether a product of the element of the first input matrix and the element of the second input matrix will equal zero (0); and
responsive to determining that the product of the element of the first input matrix and the element of the second input matrix will not equal zero (0);
provide, by the sequencer, the element of the first input matrix and the element of the second input matrix to a corresponding MAC unit of the plurality of MAC units; and
perform, by the corresponding MAC unit, a multiplication and accumulation operation using the element of the first input matrix and the element of the second input matrix.
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Accused Products
Abstract
Providing efficient multiplication of sparse matrices in matrix-processor-based devices is disclosed herein. In one aspect, a matrix processor of a matrix-processor-based device includes a plurality of sequencers coupled to a plurality of multiply/accumulate (MAC) units for performing multiplication and accumulation operations. Each sequencer determines whether a product of an element of a first input matrix to be multiplied with an element of a second input matrix has a value of zero (e.g., by determining whether the element of the first input matrix has a value of zero, or by determining whether either the element of the first input matrix or that of the second input matrix has a value of zero). If the product of the elements of the first input matrix and the second input matrix does not have a value of zero, the sequencer provides the elements to a MAC unit to perform a multiplication and accumulation operation.
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Citations
18 Claims
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1. A matrix-processor-based device comprising a matrix processor, wherein:
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the matrix processor comprises a plurality of sequencers communicatively coupled to one or more multiply/accumulate (MAC) units of a plurality of MAC units; and the matrix processor is configured to; receive a first input matrix and a second input matrix; select, by each sequencer of the plurality of sequencers, an element of the first input matrix and an element of the second input matrix to be multiplied; determine, by the sequencer, whether a product of the element of the first input matrix and the element of the second input matrix will equal zero (0); and responsive to determining that the product of the element of the first input matrix and the element of the second input matrix will not equal zero (0); provide, by the sequencer, the element of the first input matrix and the element of the second input matrix to a corresponding MAC unit of the plurality of MAC units; and perform, by the corresponding MAC unit, a multiplication and accumulation operation using the element of the first input matrix and the element of the second input matrix. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A matrix-processor-based device, comprising:
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a means for receiving a first input matrix and a second input matrix; a means for selecting an element of the first input matrix and an element of the second input matrix to be multiplied; a means for determining whether a product of the element of the first input matrix and the element of the second input matrix will equal zero (0); and a means for performing a multiplication and accumulation operation using the element of the first input matrix and the element of the second input matrix, responsive to determining that the product of the element of the first input matrix and the element of the second input matrix will not equal zero (0). - View Dependent Claims (11, 12, 13)
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14. A method for performing efficient multiplication of sparse matrices, comprising:
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receiving, by a matrix processor of a matrix-processor-based device, a first input matrix and a second input matrix; selecting, by each sequencer of a plurality of sequencers of the matrix processor, an element of the first input matrix and an element of the second input matrix to be multiplied; determining, by the sequencer, whether a product of the element of the first input matrix and the element of the second input matrix will equal zero (0); and responsive to determining that the product of the element of the first input matrix and the element of the second input matrix will not equal zero (0); providing, by the sequencer, the element of the first input matrix and the element of the second input matrix to a corresponding multiply/accumulate (MAC) unit of a plurality of MAC units of the matrix processor; and performing, by the corresponding MAC unit, a multiplication and accumulation operation using the element of the first input matrix and the element of the second input matrix. - View Dependent Claims (15, 16, 17, 18)
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Specification