NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME

• US 20190065392A1
• Filed: 08/23/2017
• Published: 02/28/2019
• Est. Priority Date: 08/23/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: EREZ, Elona, DOR, Avner, TWITTO, Moshe, KONG, Jun Jin
• Granted Patent: US 10,606,760 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

Claims

1. A memory system comprising:

a nonvolatile memory device comprising a plurality of physical sectors;

a mapping table; and

a memory controller including a plurality of hash functions, the memory controller configured to access the physical sectors using the mapping table and the hash functions,

wherein the memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

2. The memory system of claim 1, wherein the controller updates the mapping table to include entries for each of the LBAs including an index of the selected hash function and a pointer to the first entry.

3. The memory system of claim 1, wherein each hash function is configured to generate a pseudo-random number when operated on an LBA.

4. The memory system of claim 2, wherein the controller is configured to receive an input LBA and a read command from the host, access an entry of the mapping table associated with the input LBA to retrieve an index and an offset pointer, subtract the retrieved offset from the input LBA to generate a result, operate one of the hash functions identified by the retrieved index on the result to generate a second virtual address, and output data of one of the physical sectors associated with the second virtual address to the host.

5. The memory system of claim 1, wherein the nonvolatile memory is flash memory.

6. The memory system of claim 1, wherein the controller stores information in a spare region of the first physical sector indicating offsets and lengths of compressed logical sector data for each of the LBAs.

7. The memory system of claim 2, wherein the controller is configured to update the entries to indicate that logical sector data associated with each of the LBAs has been compressed.

8. The memory system of claim 2, wherein the controller is configured to receive an input LBA, store logical sector data associated with the input LBA in the memory device without compression in one of the physical sectors, and update an entry of the mapping table corresponding to the input LBA to indicate the stored logical sector data is uncompressed.

9. The memory system of claim 1, wherein the controller stores the compressed data in the first physical sector and a second physical sector among the physical sectors.

10. The memory system of claim 9, wherein the compressed data includes compressed data for one logical sector that is split across the first and second physical sectors.

11. The memory system of claim 10, wherein the controller updates the mapping table to indicate that the one logical sector is split.

12. The memory system of claim 1, further comprising a buffer temporarily storing the sequence of logical block addresses (LBAs) and the corresponding logical sector data.

13. A method of writing data to a memory system comprising:

receiving, by a memory controller, a sequence of logical block addresses (LBAs) and logical sector data for each of the LBAs, from a host;

compressing, by the memory controller, the logical sector data;

executing, by the memory controller, a selected hash function among a plurality of hash functions on a first LBA among the LBAs to generate a virtual address; and

storing, the compressed data in a first physical sector of a nonvolatile memory associated with the virtual address.

14. The method of claim 13, further comprising the memory controller updating a mapping table to include entries for each of the LBAs including an index of the selected hash function and a pointer to the first entry.

15. The method of claim 13, wherein each hash function is configured to generate a pseudo-random number when operated on an LBA.

16. The method of claim 13, further comprising the memory controller storing information in spare region of the first physical sector indicating offsets and lengths of compressed logical sector data for each of the LBAs.

17. The method of claim 14, further comprising the memory controller updating the entries to indicate that logical sector data associated with each of the LBAs has been compressed.

19. The method of claim 17, further comprising:

uncompressing, by the memory controller, the retrieved data to generate uncompressed data; and

sending, by the controller, the uncompressed data to the host.

20. The method of claim 17, wherein the retrieving of the data comprises:

determining, by the memory controller, an offset and a size of the data in the physical sector from a spare region in the physical sector; and

extracting, by the memory controller, data from the physical sector at the offset and having the size.

18. A method of reading data from a memory system comprising:

receiving, by a memory controller, a logical block address (LBA) from a host;

accessing, by the memory controller, an entry of a mapping table associated with the LBA to retrieve an index and a pointer;

generating, by the memory controller, a value by subtracting the pointer from the LBA;

executing, by the memory controller, a hash function identified by the index to generate a virtual address; and

retrieving data from a physical sector of a nonvolatile memory associated with the virtual address.