SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20190067118A1
• Filed: 10/30/2018
• Published: 02/28/2019
• Est. Priority Date: 06/09/2017
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Chun-Hao, Chen, Hsin-Yu, Lu, Chun-Tsen, Hsieh, Shou-Wei
• Granted Patent: US 10,446,448 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

Claims

1. A semiconductor device, comprising:

a substrate having a first region and a second region;

a first fin-shaped structure on the first region and a second fin-shaped structure on the second region;

a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure;

a first oxide layer on the first fin-shaped structure;

a second oxide layer on and directly contacting the first oxide layer and the STI; and

a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

2. The semiconductor device of claim 1, wherein a thickness of the first oxide layer is less than a thickness of the second oxide layer.

3. The semiconductor device of claim 1, further comprising:

a first liner on the first fin-shaped structure;

a second liner on the first liner; and

a dielectric layer on the second liner and around the first fin-shaped structure.

4. The semiconductor device of claim 3, wherein the first liner and the second liner comprise silicon oxide.

5. The semiconductor device of claim 3, wherein a thickness of the first liner is greater than a thickness of the first oxide layer.