Fill Fins for Semiconductor Devices

• US 20190067417A1
• Filed: 08/29/2017
• Published: 02/28/2019
• Est. Priority Date: 08/29/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Cheng, Kuan-Lun, Wang, Chih-Hao
• Granted Patent: US 10,403,714 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device includes a semiconductor substrate, first and second device fins extending from the semiconductor substrate, and a fill fin disposed on the semiconductor substrate and between the first and second device fins, wherein the fill fin has an opening. The semiconductor device further includes a first gate structure extending continuously from a channel region of the first device fin to a channel region of the second device fin through the opening.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

first and second device fins extending upwardly from the semiconductor substrate, each of the first and second device fins extending lengthwise in a first direction;

a fill fin disposed on the semiconductor substrate and between the first and second device fins, the fill fin including a dielectric material extending continuously along the first direction throughout the fill fin, wherein the fill fin has an opening; and

a first gate structure extending continuously from a channel region of the first device fin to a channel region of the second device fin through the opening.

2. The semiconductor device of claim 1, further comprising:

a dielectric material layer disposed between the first and second device fins and between the fill fin and the semiconductor substrate.

3. The semiconductor device of claim 2, wherein the dielectric material layer is a shallow trench isolation (STI) feature.

4. The semiconductor device of claim 1, further comprising:

a second gate structure over the first device fin; and

a third gate structure over the second device fin, wherein the second gate structure is electrically isolated from the third gate structure by the fill fin.

5. The semiconductor device of claim 1, wherein:

a top surface of the fill fin outside the opening is above top surfaces of the first and second device fins; and

a bottom surface of the fill fin is above bottom surfaces of the first and second device fins.

6. The semiconductor device of claim 5, wherein the top surface of the fill fin in the opening is below the top surfaces of the first and second device fins.

7. The semiconductor device of claim 1, wherein the fill fin includes metal oxide.

8. The semiconductor device of claim 1, wherein the first gate structure fills up the opening.

9. The semiconductor device of claim 1, wherein the opening is disposed in a topmost portion of the fill fin.

10. The semiconductor device of claim 9, wherein the opening has a vertical depth in a range from about 15 nm to about 40 nm.

25. The semiconductor device of claim 1, wherein the fill fin has a first sidewall, a second sidewall opposing the first sidewall, and a top surface in the opening extending from the first sidewall to the second sidewall, further comprising:

a dielectric layer disposed on at least one of the first and second sidewalls without extending to the top surface.

11. A device, comprising:

a device fin extending from a substrate;

a dielectric fin disposed above the substrate, a top portion of the dielectric fin having a notch;

an isolation feature disposed on sidewalls of both the device fin and the dielectric fin, wherein a portion of the isolation feature is directly under the dielectric fin; and

a gate structure engaging a top portion of the device fin and extending above the notch.

12. The device of claim 11, wherein a bottom surface of the dielectric fin is between a top surface and a bottom surface of the isolation feature.

13. The device of claim 11, wherein a bottom surface of the dielectric fin is higher than a bottom surface of the device fin.

14. The device of claim 11, wherein:

a top surface of the dielectric fin outside the notch is higher than a top surface of the device fin; and

the top surface of the dielectric fin inside the notch is lower than the top surface of the device fin.

15. The device of claim 11, wherein the gate structure includes an input/output (I/O) oxide layer on a sidewall of the dielectric fin and is free of the I/O oxide layer on a top surface of the dielectric fin inside the notch.

16. The device of claim 11, wherein the device fin and the dielectric fin have substantially the same horizontal width.

17-20. -20. (canceled)

21. A semiconductor device, comprising:

a substrate;

an isolation feature above the substrate;

a device fin extending from the substrate and through the isolation feature;

first and second fill fins disposed above the isolation feature and sandwiching the device fin, wherein the first fill fin has a trench above the isolation feature, wherein a bottom surface of the first fill fin is above a bottom surface of the second fill fin; and

a gate stack over a channel region of the device fin, wherein a portion of the gate stack fills the trench.

22. The semiconductor device of claim 21, wherein a top surface of the first fill fin outside the trench is above a top surface of the device fin.

24. The semiconductor device of claim 21, wherein a top surface of the device fin is between a top surface of the first fill fin in the trench and a top surface of the second fill fin.

23. (canceled)