INTER-POLY OXIDE IN FIELD EFFECT TRANSISTORS

• US 20190067427A1
• Filed: 12/08/2017
• Published: 02/28/2019
• Est. Priority Date: 08/24/2017
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: BURKE, Peter A., PROBST, Dean E., HOSE, Sallie J.
• Application Number:
  US15/836,328
• Publication Number:
  US 20190067427A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence

Abstract

A method of forming a shielded gate field effect transistor includes forming a trench within a substrate and depositing a shield oxide material within the trench, which is then recessed. The method further includes depositing a shield electrode material on the shield oxide material and recessing the shield oxide material within the trench to widen an upper portion of the trench. The method further includes recessing the shield electrode material thus forming a recession and depositing an inter-poly oxide material on the shield electrode material into the recession, thus filling the recession. The method further includes forming a gate electrode above the inter-poly oxide material.

Claims

1. A method of manufacturing a shielded gate field effect transistor comprising:

forming a trench within a substrate;

forming a shield oxide material within the trench;

depositing a shield electrode material on the shield oxide material;

recessing the shield electrode material within the trench;

recessing the shield oxide material within the trench to widen an upper portion of the trench;

recessing the shield electrode material thus forming a recession; and

depositing an inter-poly oxide material on the shield electrode material into the recession, thus filling the recession.

2. The method of claim 1, wherein depositing the inter-poly oxide material comprises depositing the inter-poly oxide material with a thickness of at least half of the width of the recession.

3. The method of claim 1, wherein depositing the inter-poly oxide material comprises depositing the inter-poly oxide material with a thickness between 800 angstroms and 3,000 angstroms.

4. The method of claim 1, further comprising recessing the shield electrode material before recessing the shield oxide material.

5. The method of claim 1, further comprising etching the inter-poly oxide material from the shield oxide material formed on sidewalls of the trench and a surface of the substrate.

6. The method of claim 5, further comprising etching the shield oxide material formed on sidewalls of the trench and a surface of the substrate.

7. The method of claim 1, further comprising etching the inter-poly oxide material and shield oxide material formed on sidewalls of the trench and a surface of the substrate in one etch.

8. The method of claim 1, wherein the inter-poly oxide material comprises spin-on glass.

9. The method of claim 1, further comprising doping the inter-poly oxide material to increase etch rate and etch selectivity.

10. The method of claim 9, wherein doping the inter-poly oxide material comprises doping the inter-poly oxide material with boron.

11. A shielded gate field effect transistor comprising:

a substrate;

a shield electrode;

a gate electrode;

a shield oxide between the shield electrode and the substrate; and

an inter-poly oxide between the gate electrode and the shield electrode, wherein the inter-poly oxide is at least 800 angstroms thick.

12. The transistor of claim 11, wherein the inter-poly oxide is between 800 and 3,000 angstroms thick.

13. The transistor of claim 11, wherein the inter-poly oxide comprises spin-on glass.

14. The transistor of claim 11, wherein the inter-poly oxide is doped to increase etch rate and etch selectivity.

15. The transistor of claim 14, wherein the inter-poly oxide is doped with boron.

16. The transistor of claim 11, wherein the inter-poly oxide thickness is independent of the gate electrode thickness.

17. The transistor of claim 11, wherein the inter-poly oxide thickness is at least three times the gate electrode thickness.

18. A method of manufacturing a shielded gate field effect transistor comprising:

recessing shield electrode material thus forming a recession;

depositing an inter-poly oxide material with a thickness of at least 800 angstroms on the shield electrode material into the recession, thus filling the recession; and

forming a gate electrode above the inter-poly oxide material.

19. The method of claim 18, wherein depositing the inter-poly oxide material comprises depositing the inter-poly oxide material with a thickness between 800 angstroms and 3,000 angstroms.

20. The method of claim 18, wherein depositing the inter-poly oxide material comprises depositing the inter-poly oxide material with a thickness of at least half of the width of the recession.