SIGNAL AMPLIFIER, SIGNAL RECEIVING CIRCUIT INCLUDING THE SAME, AND DEVICE INCLUDING THE SAME

• US 20190068145A1
• Filed: 05/09/2018
• Published: 02/28/2019
• Est. Priority Date: 08/24/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Soo Min
• Granted Patent: US 10,461,708 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45301 there are multiple cascaded folded or not folded common gate stages of a cascode dif amp
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03F 3/45672 Controlling the common source circuit of the differential amplifier

Abstract

A signal amplifier includes a first amplifier, a second amplifier, and an output. The first amplifier amplifies a first input signal to form a first amplified output signal. The first input signal has a common mode voltage in a first voltage range, and the first amplified output signal has a common mode voltage in a second voltage range different from the first voltage range. The second amplifier amplifies a second input signal to form a second amplified output signal. The first input signal has the common mode voltage in the second voltage range and the second amplified output signal has the common mode voltage in the second voltage range. The output outputs the first amplified output signal or the second amplified output signal as an amplified output signal.

Claims

1. A signal amplifier, comprising:

a first amplifier to amplify a first input signal to form a first amplified output signal, the first input signal having a common mode voltage in a first voltage range and the first amplified output signal having a common mode voltage in a second voltage range different from the first voltage range;

a second amplifier to amplify a second input signal to form a second amplified output signal, the first input signal having the common mode voltage in the second voltage range and the second amplified output signal having the common mode voltage in the second voltage range; and

an output to output the first amplified output signal or the second amplified output signal as an amplified output signal.

2. The signal amplifier as claimed in claim 1, wherein:

the first amplifier is to output a first bias voltage in the first voltage range,

the output is to output a second bias voltage in the second voltage range, and

the signal amplifier includes a bias controller to adjust a level of power supplied to the first amplifier and the second amplifier based on the first bias voltage and the second bias voltage.

3. The signal amplifier as claimed in claim 1, further comprising:

an enable controller to control supply power to the first amplifier or the second amplifier based on a first enable signal activated when the first input signal is input and a second enable signal activated when the second input signal is input.

4. The signal amplifier as claimed in claim 1, wherein the first amplifier includes:

a first sub-amplifier to amplify the first input signal to form an intermediate amplified output signal having a common mode voltage in the first voltage range; and

a second sub-amplifier to amplify the intermediate amplified output signal to form the first amplified output signal.

5. The signal amplifier as claimed in claim 4, further comprising:

a bias controller to adjust a level of power supplied to the first amplifier and the second amplifier based on a common mode voltage of the intermediate amplified output signal and a common mode voltage of the amplified output signal.

6. The signal amplifier as claimed in claim 4, wherein:

the first voltage range includes values closer to a source voltage than to a ground voltage,

the second voltage range includes values closer to the ground voltage than to the source voltage,

the first sub-amplifier is an n-type metal oxide semiconductor (NMOS) common source amplifier,

the second sub-amplifier is a p-type metal oxide semiconductor (PMOS) common gate amplifier, and

the second amplifier is a PMOS common source amplifier.

8. The signal amplifier as claimed in claim 4, wherein:

the first voltage range includes values closer to a ground voltage than to a source voltage,

the second voltage range includes values closer to the source voltage than to the ground voltage,

the first sub-amplifier is a PMOS common source amplifier,

the second sub-amplifier is an NMOS common gate amplifier, and

the second amplifier is an NMOS common source amplifier.

10. The signal amplifier as claimed in claim 1, wherein the first amplifier includes:

a first-type first transistor including a gate to receive one signal of the first input signal,

a first-type second transistor including a gate to receive another signal of the first input signal and a source connected to a source of the first-type first transistor;

a first resistor and a second resistor connected between a drain of the first-type first transistor and a drain of the first-type second transistor;

a second-type first transistor including a source connected to the drain of the first-type first transistor, a drain connected to a first output terminal to output one signal of the amplified output signal, and a gate to receive a common mode voltage of the amplified output signal; and

a second-type second transistor including a source connected to the drain of the first-type second transistor, a drain connected to a second output terminal to output another signal of the amplified output signal, and a gate connected to the gate of the second-type first transistor.

11. The signal amplifier as claimed in claim 10, wherein the second amplifier includes:

a second-type third transistor including a gate to receive one signal of the second input signal and a drain connected to the first output terminal; and

a second-type fourth transistor including a gate to receive another signal of the second input signal, a drain connected to the second output terminal, and a source connected to the source of the second-type third transistor.

12. The signal amplifier as claimed in claim 11, wherein the output includes a third resistor and a fourth resistor connected between the first output terminal and the second output terminal.

13. The signal amplifier as claimed in claim 12, wherein:

the first amplifier is to output a voltage of a node between the first resistor and the second resistor as a first bias voltage,

the output is to output a voltage of a node between the third resistor and the fourth resistor as a second bias voltage, and

the signal amplifier includes a bias controller to control a magnitude of an electric current input to the first amplifier or the second amplifier or a magnitude of an electric current output from the first amplifier or the second amplifier based on the first bias voltage and the second bias voltage.

7. (canceled)

9. (canceled)

14-34. -34. (cancelled)

35. A signal amplifier, comprising:

a first type folded-cascode amplifying part configured to receive a first input signal pair and output a first amplified output signal pair in response to first state of an enable signal;

a second type common source amplifying part configured to receive a second input signal pair and output a second amplified output signal pair in response to second stage of the enable signal; and

an output part comprising a load for the first type folded-cascode amplifying part and the second type common source amplifying part, and configured to output one of the first amplified output signal pair and the second amplified output signal pair as an amplified output signal pair.

37. The signal amplifier as claimed in claim 35, wherein:

the first type folded-cascode amplifying part comprises;

an n-type metal oxide semiconductor (NMOS) common source amplifier to amplify the first input signal pair to form an intermediate amplified output signal pair; and

a p-type metal oxide semiconductor (PMOS) common gate amplifier to amplify the intermediate amplified output signal pair to form the first amplified output signal pair, and

the second amplifier is a PMOS common source amplifier.

38. The signal amplifier as claimed in claim 37, wherein:

the NMOS common source amplifier is to output a first bias voltage in a first voltage range,

the output is to output a second bias voltage in a second voltage range different from the first voltage range,

the signal amplifier further comprises

a first bias controller to adjust a level of power supplied to the NMOS common source amplifier based on the first bias voltage;

a second bias controller to adjust a level of power supplied to the PMOS common gate amplifier based on the second bias voltage; and

a third bias controller to adjust a level of power supplied to the PMOS common source amplifier based on the second bias voltage, and

the first voltage range includes values closer to a source voltage than to a ground voltage, and the second voltage range includes values closer to the ground voltage than to the source voltage.

39. The signal amplifier as claimed in claim 35, wherein:

the first type folded-cascode amplifying part comprises;

an p-type metal oxide semiconductor (PMOS) common source amplifier to amplify the first input signal pair to form an intermediate amplified output signal pair; and

a n-type metal oxide semiconductor (NMOS) common gate amplifier to amplify the intermediate amplified output signal pair to form the first amplified output signal pair, and

the second amplifier is a NMOS common source amplifier.

40. The signal amplifier as claimed in claim 39, wherein:

the PMOS common source amplifier is to output a first bias voltage in a first voltage range,

the output is to output a second bias voltage in a second voltage range different from the first voltage range,

the signal amplifier further comprises

a first bias controller to adjust a level of power supplied to the PMOS common source amplifier based on the first bias voltage;

a second bias controller to adjust a level of power supplied to the NMOS common gate amplifier based on the second bias voltage; and

a third bias controller to adjust a level of power supplied to the NMOS common source amplifier based on the second bias voltage, and

the first voltage range includes values closer to a ground voltage than to a source voltage, and the second voltage range includes values closer to the source voltage than to the ground voltage.

36. (canceled)

41. A signal receiving circuit, comprising:

a signal amplifying portion comprising a first type folded-cascode amplifier configured to receive a first input signal pair and output a first amplified output signal pair in response to first state of an enable signal, a second type common source amplifier configured to receive a second input signal pair and output a second amplified output signal pair in response to second stage of the enable signal, and an output comprising a load for the first type folded-cascode amplifying part and the second type common source amplifying part, and configured to output one of the first amplified output signal pair and the second amplified output signal pair as an amplified output signal pair; and

an output portion configured to output an output signal based on the amplified output signal pair, wherein an input terminal of the output portion comprises transistors of a same conductivity type.

42. A signal receiving circuit of claim 41, wherein:

the first type folded-cascode amplifier comprises;

an n-type metal oxide semiconductor (NMOS) common source amplifier to amplify the first input signal pair to form an intermediate amplified output signal pair; and

a p-type metal oxide semiconductor (PMOS) common gate amplifier to amplify the intermediate amplified output signal pair to form the first amplified output signal pair,

the second amplifier is a PMOS common source amplifier, and

the input terminal of the output portion comprises PMOS transistors.

45. A signal receiving circuit of claim 41, wherein:

the first type folded-cascode amplifier comprises;

an p-type metal oxide semiconductor (PMOS) common source amplifier to amplify the first input signal pair to form an intermediate amplified output signal pair; and

a n-type metal oxide semiconductor (NMOS) common gate amplifier to amplify the intermediate amplified output signal pair to form the first amplified output signal pair,

the second amplifier is a NMOS common source amplifier, and

the input terminal of the output portion comprises MMOS transistors.

48. A signal receiving circuit of claim 41, further comprising:

a switching portion configured to output a reception signal as the first input signal in response to first state of the enable signal and to output the reception signal as the second input signal in response to second state of the enable signal.

43-44. -44. (canceled)

46-47. -47. (canceled)