GOA CIRCUIT FOR PREVENTING CLOCK SIGNALS FROM MISSING

• US 20190073978A1
• Filed: 09/15/2017
• Published: 03/07/2019
• Est. Priority Date: 09/04/2017
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Shi, Longqiang, Chen, Shujhih
• Granted Patent: US 10,515,601 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present invention involves a GOA circuit for preventing clock signals from missing. The GOA circuit comprises a plurality of cascaded GOA units. The N-th stage GOA unit comprises a pull-high stage-transfer unit, a pull-down unit, and a pull-down sustain unit, which are respectively connected with a first node (Q(N)) and a gate signal output terminal (G(N)) of the N-th stage GOA unit. The pull-high control unit is connected with the first node (Q(N)) of the N-th stage GOA unit. From a specific stage, each of the GOA unit further comprises an additional circuit for preventing clock signals from missing. The additional circuit is connected with the pull-down sustain unit. When the clock signal is missing, the additional circuit utilizes the start signal (STV), a first low-frequency clock signal (LC1), and the second low-frequency clock signal (LC2) which are capable of lowering the potential of the first node (Q(N)) of the N-th stage GOA unit. The GOA circuit for preventing clock signals from missing of the present invention, which is capable of solving the problem that the display signal is damaged due to the disappearance of the clock signal.

Claims

1. A GOA circuit for preventing clock signals from missing, comprising:

a plurality of cascaded GOA units, wherein the N-th stage GOA unit controls charging of the N-th stage horizontal scanning line, the N-th stage GOA unit comprises a pull-high control unit, a pull-high stage-transfer unit, a pull-down unit, and a pull-down sustain unit;

the pull-high stage-transfer unit, the pull-down unit and the pull-down sustain unit are respectively connected with a first node and a gate signal output terminal of the N-th stage GOA unit, two alternative functional pull-down modules of the pull-down sustain unit are respectively connected with a first low-frequency clock signal and a second low-frequency clock signal, the pull-high control unit is connected with the first node of the N-th stage GOA unit;

from a specific stage, each of the GOA unit further comprises an additional circuit for preventing clock signals from missing, the additional circuit is connected with a start signal, the first low-frequency clock signal, and the second low-frequency clock signal;

when the clock signal is missing and a next frame is turned on, the start signal passed through with a high potential, the first low-frequency clock signal and the second low-frequency clock signal which have reversed potential are capable of controlling the potential of the first node of the N-th stage GOA unit.

2. The GOA circuit for preventing clock signals from missing according to claim 1, wherein the pull-down sustain unit comprises:

a first thin film transistor, a gate electrode of the first thin film transistor is connected with a second node of the N-th stage GOA unit, a source electrode and a drain electrode of the first thin film transistor are respectively connected with the gate signal output terminal and a constant low-voltage signal;

a second thin film transistor, a gate electrode of the second thin film transistor is connected with a third node of the N-th stage GOA unit, a source electrode and a drain electrode of second thin film transistor are respectively connected with the gate signal output terminal and the constant low-voltage signal;

a third thin film transistor, a gate electrode of the third thin film transistor is connected with the second node, a source electrode and a drain electrode of the third thin film transistor are respectively connected with the first node and the constant low-voltage signal;

a fourth thin film transistor, a gate electrode of the fourth thin film transistor is connected with the third node, a source electrode and a drain electrode of the fourth thin film transistor are respectively connected with the first node and the constant low-voltage signal;

a fifth thin film transistor, a gate electrode of the fifth thin film transistor is connected with the first low-frequency clock signal, a source electrode and a drain electrode of the fifth thin film transistor are respectively connected with the first low-frequency clock signal and a gate electrode of a sixth thin film transistor;

the sixth thin film transistor, a source electrode and a drain electrode of the sixth thin film transistor are respectively connected with the first low-frequency clock signal and the second node;

a seventh thin film transistor, a gate electrode of the seventh thin film transistor is connected with the first node, a source electrode and a drain electrode of the seventh thin film transistor are respectively connected with the constant low-voltage signal and the gate electrode of the sixth thin film transistor;

an eighth thin film transistor, a gate electrode of the eighth thin film transistor is connected with the first node, a source electrode and a drain electrode of the eighth thin film transistor are respectively connected with the constant low-voltage signal and the second node;

a ninth thin film transistor, a gate electrode of the ninth thin film transistor is connected with the second low-frequency clock signal, a source electrode and a drain electrode of the ninth thin film transistor are respectively connected with the second low-frequency clock signal and a gate electrode of a tenth thin film transistor;

the tenth thin film transistor, a source electrode and a drain electrode of the tenth thin film transistor are respectively connected with the second low-frequency clock signal and the third node;

an eleventh thin film transistor, a gate electrode of the eleventh thin film transistor is connected with the first node, a source electrode and a drain electrode of the eleventh thin film transistor are respectively connected the constant low-voltage signal and the gate of the tenth thin film transistor;

a twelfth thin film transistor, a gate electrode of the twelfth thin film transistor is connected with the first node, a source electrode and a drain electrode of the twelfth thin film transistor are respectively connected with the constant low-voltage signal and the third node.

3. The GOA circuit for preventing clock signals from missing according to claim 1, wherein the additional circuit comprises:

a thirteenth thin film transistor, a gate electrode of the thirteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the thirteenth thin film transistor are respectively connected with the first node and a gate of a fourteenth thin film transistor;

the fourteenth thin film transistor, a source electrode and a drain electrode of the fourteenth thin film transistor are respectively connected with the gate of the fourteenth thin film transistor and the first low-frequency clock signal;

a fifteenth thin film transistor, a gate electrode of the fifteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the fifteenth thin film transistor are respectively connected with the first node and a gate electrode of a sixteenth thin film transistor;

the sixteenth thin film transistor, a source electrode and a drain electrode of the sixteenth thin film transistor are respectively connected with the gate of the sixteenth thin film transistor and the second low-frequency clock signal.

4. The GOA circuit for preventing clock signals from missing according to claim 2, wherein the additional circuit comprises:

a seventeenth thin film transistor, a gate electrode of the seventeenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the seventeenth thin film transistor are respectively connected with the first low-frequency clock signal and the second node; and

an eighteenth thin film transistor, a gate electrode of the eighteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the eighteenth thin film transistor are respectively connected with the second low-frequency clock signal and the third node.

5. The GOA circuit for preventing clock signals from missing according to claim 2, wherein the additional circuit comprises:

a seventeenth thin film transistor, a gate electrode of the seventeenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the seventeenth thin film transistor are respectively connected with the first low-frequency clock signal and the second node;

an eighteenth thin film transistor, a gate electrode of the eighteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the eighteenth thin film transistor are respectively connected with the second low-frequency clock signal and the third node; and

a nineteenth thin film transistor, a gate electrode of the nineteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the nineteenth thin film transistor are respectively connected with the second node and the third node.

6. The GOA circuit for preventing clock signals from missing according to claim 1, wherein the pull-high control unit comprises a twentieth thin film transistor;

for top four GOA units, a gate of the twentieth thin film transistor is connected with the start signal, and a source electrode and a drain electrode of the twentieth thin film transistor are respectively connected with the start signal and the first node.

7. The GOA circuit for preventing clock signals from missing according to claim 6, wherein from a fifth stage GOA unit, the gate of the twentieth thin film transistor is connected with a stage-transfer signal output terminal of a (N−

4)th stage GOA unit, and the source electrode and the drain electrode of the twentieth thin film transistor are respectively connected with the stage-transfer signal output terminal and the first node.

8. The GOA circuit for preventing clock signals from missing according to claim 6, wherein from a ninth stage, each of the GOA unit comprises the additional circuit for preventing clock signals from missing.

9. The GOA circuit for preventing clock signals from missing according to claim 1, wherein the pull-high stage-transfer unit comprises:

a twenty-first thin film transistor, a gate of the twenty-first thin film transistor is connected with the first node, and a source electrode and a drain electrode of the twenty-first thin film transistor are respectively connected with the gate signal output terminal and a clock signal of a N-th stage GOA unit;

a twenty-second thin film transistor, a gate of the twenty-second thin film transistor is connected with the first node, and a source electrode and a drain electrode of the twenty-second thin film transistor are respectively connected with a stage-transfer signal output terminal of the N-th stage GOA unit and a clock signal of the N-th stage GOA unit; and

a bootstrap capacitor comprises two terminals are respectively connected with the first node and the gate signal output terminal.

10. The GOA circuit for preventing clock signals from missing according to claim 1, wherein the pull-down unit comprises:

a twenty-third thin film transistor, a gate of the twenty-third thin film transistor is connected with a stage-transfer signal output terminal of the (N+4)th stage GOA unit, and a source electrode and a drain electrode of the twenty-third thin film transistor are respectively connected with the first node and the constant low-voltage signal; and

a twenty-fourth thin film transistor, a gate of the twenty-fourth thin film transistor is connected with the stage-transfer signal output terminal of the (N+4)th stage GOA unit, and a source electrode and a drain electrode of the twenty-fourth thin film transistor are respectively connected with the gate signal output terminal and the constant low-voltage signal.

11. A GOA circuit for preventing clock signals from missing, comprising:

a plurality of cascaded GOA units, wherein the N-th stage GOA unit controls charging of the N-th stage horizontal scanning line, the N-th stage GOA unit comprises a pull-high control unit, a pull-high stage-transfer unit, a pull-down unit, and a pull-down sustain unit;

the pull-high stage-transfer unit, the pull-down unit and the pull-down sustain unit are respectively connected with a first node and a gate signal output terminal of the N-th stage GOA unit, two alternative functional pull-down modules of the pull-down sustain unit are respectively connected with a first low-frequency clock signal and a second low-frequency clock signal, the pull-high control unit is connected with the first node of the N-th stage GOA unit;

from a specific stage, each of the GOA unit further comprises an additional circuit for preventing clock signals from missing, the additional circuit is connected with a start signal, the first low-frequency clock signal, and the second low-frequency clock signal;

when the clock signal is missing and a next frame is turned on, the start signal passed through with a high potential, the first low-frequency clock signal and the second low-frequency clock signal which have reversed potential are capable of controlling the potential of the first node of the N-th stage GOA unit;

wherein the pull-down sustain unit comprises;

a first thin film transistor, a gate electrode of the first thin film transistor is connected with a second node of the N-th stage GOA unit, a source electrode and a drain electrode of the first thin film transistor are respectively connected with the gate signal output terminal and a constant low-voltage signal;

a second thin film transistor, a gate electrode of the second thin film transistor is connected with a third node of the N-th stage GOA unit, a source electrode and a drain electrode of second thin film transistor are respectively connected with the gate signal output terminal and the constant low-voltage signal;

a third thin film transistor, a gate electrode of the third thin film transistor is connected with the second node, a source electrode and a drain electrode of the third thin film transistor are respectively connected with the first node and the constant low-voltage signal;

a fourth thin film transistor, a gate electrode of the fourth thin film transistor is connected with the third node, a source electrode and a drain electrode of the fourth thin film transistor are respectively connected with the first node and the constant low-voltage signal;

a fifth thin film transistor, a gate electrode of the fifth thin film transistor is connected with the first low-frequency clock signal, a source electrode and a drain electrode of the fifth thin film transistor are respectively connected with the first low-frequency clock signal and a gate electrode of a sixth thin film transistor;

the sixth thin film transistor, a source electrode and a drain electrode of the sixth thin film transistor are respectively connected with the first low-frequency clock signal and the second node;

a seventh thin film transistor, a gate electrode of the seventh thin film transistor is connected with the first node, a source electrode and a drain electrode of the seventh thin film transistor are respectively connected with the constant low-voltage signal and the gate electrode of the sixth thin film transistor;

an eighth thin film transistor, a gate electrode of the eighth thin film transistor is connected with the first node, a source electrode and a drain electrode of the eighth thin film transistor are respectively connected with the constant low-voltage signal and the second node;

a ninth thin film transistor, a gate electrode of the ninth thin film transistor is connected with the second low-frequency clock signal, a source electrode and a drain electrode of the ninth thin film transistor are respectively connected with the second low-frequency clock signal and a gate electrode of a tenth thin film transistor;

the tenth thin film transistor, a source electrode and a drain electrode of the tenth thin film transistor are respectively connected with the second low-frequency clock signal and the third node;

an eleventh thin film transistor, a gate electrode of the eleventh thin film transistor is connected with the first node, a source electrode and a drain electrode of the eleventh thin film transistor are respectively connected the constant low-voltage signal and the gate of the tenth thin film transistor;

a twelfth thin film transistor, a gate electrode of the twelfth thin film transistor is connected with the first node, a source electrode and a drain electrode of the twelfth thin film transistor are respectively connected with the constant low-voltage signal and the third node;

wherein the pull-high control unit comprises a twentieth thin film transistor;

for top four GOA units, a gate of the twentieth thin film transistor is connected with the start signal, and a source electrode and a drain electrode of the twentieth thin film transistor are respectively connected with the start signal and the first node;

wherein from a fifth stage GOA unit, the gate of the twentieth thin film transistor is connected with a stage-transfer signal output terminal of a (N−

4)th stage GOA unit, and the source electrode and the drain electrode of the twentieth thin film transistor are respectively connected with the stage-transfer signal output terminal and the first node;

wherein from a ninth stage, each of the GOA unit comprises the additional circuit for preventing clock signals from missing;

wherein the pull-high stage-transfer unit comprises;

a twenty-first thin film transistor, a gate of the twenty-first thin film transistor is connected with the first node, and a source electrode and a drain electrode of the twenty-first thin film transistor are respectively connected with the gate signal output terminal and a clock signal of a N-th stage GOA unit;

a twenty-second thin film transistor, a gate of the twenty-second thin film transistor is connected with the first node, and a source electrode and a drain electrode of the twenty-second thin film transistor are respectively connected with a stage-transfer signal output terminal of the N-th stage GOA unit and a clock signal of the N-th stage GOA unit; and

a bootstrap capacitor comprises two terminals are respectively connected with the first node and the gate signal output terminal.

12. The GOA circuit for preventing clock signals from missing according to claim 11, wherein the additional circuit comprises:

a thirteenth thin film transistor, a gate electrode of the thirteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the thirteenth thin film transistor are respectively connected with the first node and a gate of a fourteenth thin film transistor;

the fourteenth thin film transistor, a source electrode and a drain electrode of the fourteenth thin film transistor are respectively connected with the gate of the fourteenth thin film transistor and the first low-frequency clock signal;

a fifteenth thin film transistor, a gate electrode of the fifteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the fifteenth thin film transistor are respectively connected with the first node and a gate electrode of a sixteenth thin film transistor;

the sixteenth thin film transistor, a source electrode and a drain electrode of the sixteenth thin film transistor are respectively connected with the gate of the sixteenth thin film transistor and the second low-frequency clock signal.

13. The GOA circuit for preventing clock signals from missing according to claim 11, wherein the additional circuit comprises:

a seventeenth thin film transistor, a gate electrode of the seventeenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the seventeenth thin film transistor are respectively connected with the first low-frequency clock signal and the second node; and

an eighteenth thin film transistor, a gate electrode of the eighteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the eighteenth thin film transistor are respectively connected with the second low-frequency clock signal and the third node.

14. The GOA circuit for preventing clock signals from missing according to claim 11, wherein the additional circuit comprises:

a seventeenth thin film transistor, a gate electrode of the seventeenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the seventeenth thin film transistor are respectively connected with the first low-frequency clock signal and the second node;

an eighteenth thin film transistor, a gate electrode of the eighteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the eighteenth thin film transistor are respectively connected with the second low-frequency clock signal and the third node; and

a nineteenth thin film transistor, a gate electrode of the nineteenth thin film transistor is connected with the start signal, a source electrode and a drain electrode of the nineteenth thin film transistor are respectively connected with the second node and the third node.

15. The GOA circuit for preventing clock signals from missing according to claim 11, wherein the pull-down unit comprises:

a twenty-third thin film transistor, a gate of the twenty-third thin film transistor is connected with a stage-transfer signal output terminal of the (N+4)th stage GOA unit, and a source electrode and a drain electrode of the twenty-third thin film transistor are respectively connected with the first node and the constant low-voltage signal; and

a twenty-fourth thin film transistor, a gate of the twenty-fourth thin film transistor is connected with the stage-transfer signal output terminal of the (N+4)th stage GOA unit, and a source electrode and a drain electrode of the twenty-fourth thin film transistor are respectively connected with the gate signal output terminal and the constant low-voltage signal.