MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY

• US 20190074263A1
• Filed: 09/05/2017
• Published: 03/07/2019
• Est. Priority Date: 09/05/2017
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Costa, Julio C., Maxim, George
• Granted Patent: US 10,784,233 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/80904 by means of an encapsulation layer or foil
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 Optical coupling
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/14215 : Low-noise amplifier [LNA]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Claims

1. An apparatus comprising:

a module substrate having an upper surface;

a first thinned flip chip die comprising a first device layer, a first dielectric layer and a plurality of first interconnects, wherein;

the first device layer includes a first coupling component embedded therein;

the first dielectric layer resides over an upper surface of the first device layer; and

the plurality of first interconnects extends from a lower surface of the first device layer and is coupled to the upper surface of the module substrate;

a first mold compound residing over the upper surface of the module substrate, surrounding the first thinned flip chip die, and extending above an upper surface of the first thinned flip chip die to define a first opening within the first mold compound and vertically above the first thinned flip chip die, wherein;

the first mold compound does not reside over the first thinned flip chip die and provides vertical walls of the first opening, which are aligned with edges of the first thinned flip chip die in both X-direction and Y-direction;

the X-direction and the Y-direction are parallel to the upper surface of the module substrate, and the X-direction and the Y-direction are orthogonal to each other; and

the upper surface of the first thinned flip chip die is exposed at a bottom of the first opening; and

a second die stacked with the first thinned flip chip die and in the first opening, wherein;

the second die comprises a second coupling component embedded therein; and

the second coupling component is mirrored to the first coupling component.

2. The apparatus of claim 1 wherein the second die has at least one of an X-direction dimension and a Y-direction dimension essentially the same as the first thinned flip chip die, such that the second die stacked in the first opening is self-aligned with the first thinned flip chip die.

3. The apparatus of claim 2 wherein the second die has both the X-direction dimension and the Y-direction dimension essentially the same as the first thinned flip chip die.

4. The apparatus of claim 1 wherein the first thinned flip chip die and the second die do not have electrical connections.

5. The apparatus of claim 4 wherein a distance between the first coupling component and the second coupling component is between 0.1 μ

m and 100 μ

m.

6. The apparatus of claim 4 wherein:

the first coupling component and the second coupling component are inductive components; and

the first coupling component is magnetically coupled to the second coupling component.

7. The apparatus of claim 4 wherein:

the first coupling component and the second coupling component are photonic components; and

the first coupling component is optically coupled to the second coupling component.

8. The apparatus of claim 4 wherein the first thinned flip chip die and the second die convey signals to each other by one type of energy from a group consisting of electro-magnetic energy, optical energy, thermal energy, vibration mechanical energy, acoustic wave energy, and X-ray energy.

9. The apparatus of claim 1 wherein the first thinned flip chip die is formed from a silicon-on-insulator (SOI) die, wherein the first device layer of the first thinned flip chip die is a silicon epitaxy layer with integrated electronic components of the SOI die, and the first dielectric layer of the first thinned flip chip die is a buried oxide layer of the SOI die.

10. The apparatus of claim 1 further comprising a second mold compound encapsulating the second die.

11. The apparatus of claim 10 wherein the first mold compound is formed from a same material as the second mold compound.

12. The apparatus of claim 10 wherein the first mold compound and the second mold compound are formed from different materials.

13. The apparatus of claim 10 wherein:

the first opening includes a lower region and an upper region that resides over the lower region;

the second die resides within the lower region of the first opening; and

the second mold compound fills the upper region of the first opening and is in contact with the second die.

14. The apparatus of claim 10 wherein:

the second die extends vertically beyond the first opening; and

the second mold compound resides over the first mold compound and encapsulates the second die.

15. The apparatus of claim 1 wherein:

an upper surface of the second die and an upper surface of the first mold compound are coplanar; and

a coating layer is applied over the upper surface of the first mold compound to encapsulate the second die.

16. The apparatus of claim 1 wherein:

the second die is a thinned die that comprises a second device layer and a second dielectric layer over the second device layer;

the second device layer resides directly over the upper surface of the first thinned flip chip die; and

the second coupling component is embedded in the second device layer.

17. The apparatus of claim 16 wherein:

the first thinned flip chip die is formed from a first SOI die, wherein the first device layer of the first thinned flip chip die is a first silicon epitaxy layer with integrated electronic components of the first SOI die, and the first dielectric layer of the first thinned flip chip die is a first buried oxide layer of the first SOI die; and

the second die is formed from a second SOI die, wherein the second device layer of the second die is a second silicon epitaxy layer with integrated electronic components of the second SOI die, and the second dielectric layer of the second die is a second buried oxide layer of the second SOI die.

18. The apparatus of claim 1 further comprises a third die stacked with the first thinned flip chip die and the second die, wherein:

the first opening includes a lower region and an upper region that resides over the lower region;

the second die resides within the lower region of the first opening; and

the third die resides over the second die and in the upper region of the first opening.

19. The apparatus of claim 18 wherein:

the second die is a thinned die that comprises a second device layer and a second dielectric layer over the second device layer;

the second device layer resides directly over the upper surface of the first thinned flip chip die;

the second coupling component is embedded in the second device layer;

the third die is a thinned die that comprises a third device layer and a third dielectric layer over the third device layer; and

the third device layer resides directly over an upper surface of the second die.

20. The apparatus of claim 18 further comprising a second mold compound encapsulating the third die.

21. The apparatus of claim 1 further comprising a third thinned flip chip die and a fourth die, wherein:

the third thinned flip chip die comprises a second device layer, a second dielectric layer and a plurality of second interconnects;

the second device layer includes a third coupling component embedded therein;

the second dielectric layer resides over an upper surface of the second device layer;

the plurality of second interconnects extends from a lower surface of the second device layer and is coupled to the upper surface of the module substrate;

the first mold compound surrounds the third thinned flip chip die and extends above an upper surface of the third thinned flip chip die to define a second opening within the first mold compound and over the third thinned flip chip die, wherein the upper surface of the third thinned flip chip die is exposed at a bottom of the second opening; and

the fourth die is stacked with the third thinned flip chip die and in the second opening;

the fourth die comprises a fourth coupling component embedded therein; and

the fourth coupling component is mirrored to the third coupling component.

22. The apparatus of claim 21 further comprising a second mold compound encapsulating the second die and the fourth die.