ARRAY SUBSTRATE, TOUCH DISPLAY PANEL AND TOUCH DISPLAY DEVICE

• US 20190079625A1
• Filed: 11/11/2018
• Published: 03/14/2019
• Est. Priority Date: 06/29/2018
• Status: Active Grant

• Current Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Original Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Inventors: WANG, Yu, XIE, Zhenqing, SUN, Ying, LIU, Bingping, XU, Yumin, CHEN, Guozhao, HUANG, Min
• Granted Patent: US 10,976,845 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes

Abstract

An array substrate, a touch display panel and a touch display device are provided. In the array substrate, the number of inverters in a second buffer unit is smaller than the number of inverters in a first buffer unit, or a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit, or the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit and the size of the inverter in the second buffer unit is smaller than the size of the inverter in the first buffer unit.

Claims

1. An array substrate comprising:

a display area; and

non-display areas surrounding the display area, wherein

at least one edge of the array substrate has i notch, i is integer greater than or equal to 1;

the display area comprises notch display areas located at two sides of the notch and a regular display area, the regular display area comprises a plurality of first scan lines extending along a first direction, and each of the notch display areas comprises a plurality of second scan lines extending along the first direction;

the non-display areas at two opposite sides of the regular display area along the first direction are respectively a first non-display area and a second non-display area, the non-display areas at two opposite sides of each of the notch display areas along the first direction are respectively a third non-display area and a fourth non-display area, the third non-display area is at a side of the notch display area close to the first non-display area, and the fourth non-display area is at a side of the notch display area close to the second non-display area;

each of the first non-display area and the second non-display area is provided with first shift register units connected in cascade, each of the third non-display area and the fourth non-display area is provided with second shift register units connected in cascade, the first shift register units in the first non-display area are connected in cascade with the second shift register units in the third non-display area adjacent to the first non-display area, the second shift register units in adjacent third non-display areas are connected in cascade, the first shift register units in the second non-display area are connected in cascade with the second shift register units in the fourth non-display area adjacent to the second non-display area, and the second shift register units in adjacent fourth non-display areas are connected in cascade; and

each of the first shift register units comprises a first buffer unit, each of the second shift register units comprises a second buffer unit;

the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit;

or a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit;

or the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit, and a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit.

2. The array substrate according to claim 1, wherein the first shift register units are connected to the first scan lines respectively, and the second shift register units are connected to the second scan lines respectively;

and

two adjacent first scan lines are respectively connected to the first shift register unit in the first non-display area and the first shift register unit in the second non-display area, and two adjacent second scan lines are respectively connected to the second shift register unit in the third non-display area and the second shift register unit in the fourth non-display area.

3. The array substrate according to claim 2, wherein a ratio of the number of inverters in any first buffer unit to the number of inverters in any second buffer unit is positively correlated with a ratio of a length of the first scan line connected with the first buffer unit to a length of the second scan line connected with the second buffer unit.

4. The array substrate according to claim 3, wherein the ratio of the number of inverters in the first buffer unit to the number of inverters in the second buffer unit ranges from x to x(x+1)/2, where x is equal to the ratio of the length of the first scan line to the length of the second scan line.

5. The array substrate according to claim 2, wherein the size of the inverter in the second buffer unit being smaller than the size of the inverter in the first buffer unit comprises:

a width-to-length ratio of a transistor constituting the inverter in the second buffer unit being smaller than a width-to-length ratio of a transistor constituting the inverter in the first buffer unit.

6. The array substrate according to claim 5, wherein a ratio of a width-to-length ratio of a transistor constituting the inverter in any first buffer unit to a width-to-length ratio of a transistor constituting the inverter in any second buffer unit is positively correlated with a ratio of a length of the first scan line connected with the first buffer unit to a length of the second scan line connected with the second buffer unit.

7. The array substrate according to claim 6, wherein the ratio of the width-to-length ratio of a transistor constituting the inverter in the first buffer unit to the width-to-length ratio of a transistor constituting the inverter in the second buffer unit ranges from x to x(x+1)/2, where x is equal to the ratio of the length of the first scan line to the length of the second scan line.

8. The array substrate according to claim 4, wherein x is equal to 3.

9. The array substrate according to claim 8, wherein, in any two notch display areas, the lengths of the second scan lines in a same row are equal, and the lengths of the second scan lines in different rows are equal.

10. The array substrate according to claim 9, wherein the notch has a shape of a rectangular.

11. The array substrate according to claim 8, wherein, in the notch display areas located at two sides of the notch, the lengths of the second scan lines in a same row are equal, and the lengths of the second scan lines in different rows are not equal.

12. The array substrate according to claim 11, wherein the notch has a shape of an isosceles triangle or an isosceles trapezoid.

13. The array substrate according to claim 1, wherein

the notch is at an edge of a side of the array substrate where a driver chip is arranged;

or the notch is at an edge of a side of the array substrate opposite to a side of the array substrate where a driver chip is arranged;

or the notches are at an edge of a side of the array substrate where a driver chip is arranged, and at an edge of a side of the array substrate opposite to the side of the array substrate where a driver chip is arranged.

14. The array substrate according to claim 13, wherein the edge of the side of the array substrate where a driver chip is arranged has one or two notches;

and

the edge of the side of the array substrate, opposite to the side of the array substrate where a driver chip is arranged, has one or two notches.

15. The array substrate according to claim 1, wherein each of the first shift register unit and the second shift register unit further comprises a latch unit, a NAND gate unit and a reset unit, wherein

an input terminal of the latch unit receives a shift register signal, a clock signal terminal of the latch unit is connected to a first clock signal line, an output terminal of the latch unit is electrically connected to an input terminal of the NAND gate unit and an input terminal of a shift register in a next stage;

a clock signal terminal of the NAND gate unit is electrically connected to a second clock signal line, an output terminal of the NAND gate unit is electrically connected to an input terminal of the first buffer unit or an input terminal of the second buffer unit;

an output terminal of the first buffer unit is electrically connected to an output terminal of the first shift register unit, and an output terminal of the second buffer unit is electrically connected to an output terminal of the second shift register unit; and

an input terminal of the reset unit is electrically connected to a reset signal line, and an output terminal of the reset unit is electrically connected to a reset terminal of the latch unit.

16. The array substrate according to claim 15, wherein the first buffer unit comprises m inverters being in connected, and the second buffer unit comprises n inverters being in connected, where in is greater than n;

in the first buffer unit, an input terminal of the first inverter is electrically connected to the output terminal of the NAND gate unit, and an output terminal of the last inverter is electrically connected to the output terminal of the first shift register unit; and

in the second buffer unit, an input terminal of the first inverter is electrically connected to the output terminal of the NAND gate unit, and an output terminal of the last inverter is electrically connected to the output terminal of the second shift register unit.

17. The array substrate according to claim 16, wherein

the first buffer unit comprises a first inverter, a second inverter and a third inverter, wherein an input terminal of the first inverter is electrically connected to the output terminal of the NAND gate unit, an output terminal of the first inverter is electrically connected to an input terminal of the second inverter, an input terminal of the third inverter is electrically connected to an output terminal of the second inverter, an output terminal of the third inverter is electrically connected to the output terminal of the first shift register unit;

and

the second buffer unit comprises a sixth inverter, wherein an input terminal of the sixth inverter is electrically connected to the output terminal of the NAND gate unit, an output terminal of the sixth inverter is electrically connected to the output terminal of the second shift register unit.

18. The array substrate according to claim 15, wherein

the latch unit comprises a fourth inverter, a first clock inverter and a second clock inverter, wherein an input terminal of the fourth inverter is electrically connected to the first clock signal line, an output terminal of the fourth inverter is electrically connected to a clock input terminal of the first clock inverter and a control terminal of the second clock inverter;

an input terminal of the first clock inverter receives the shift register signal, an output terminal of the first clock inverter is electrically connected to an output terminal of the second clock inverter, and a control terminal of the first clock inverter is electrically connected to the first clock signal line;

an input terminal of the second clock inverter is electrically connected to the output terminal of the latch unit, and a clock input terminal of the second clock inverter is electrically connected to the first clock signal line;

the NAND gate unit comprises a NAND gate circuit, wherein a first input terminal of the NAND gate circuit is electrically connected to the second clock signal line, a second input terminal of the NAND gate circuit is electrically connected to the output terminal of the latch unit, an output terminal of the NAND gate circuit is electrically connected to the input terminal of the first buffer unit or the input terminal of the second buffer unit; and

the reset unit comprises a fifth inverter and a first switch transistor, wherein an input terminal of the fifth inverter is electrically connected to the output terminal of the first clock inverter, an output terminal of the fifth inverter is electrically connected to the input terminal of the NAND gate unit and the input terminal of the shift register in the next stage, a control terminal of the first switch transistor is electrically connected to the reset signal line, and an output terminal of the first switch transistor is electrically connected to the input terminal of the NAND gate unit.

19. A touch display panel comprising an array substrate, the array substrate comprising:

a display area; and

non-display areas surrounding the display area, wherein

at least one edge of the array substrate has i notch, i is an integer greater than or equal to 1;

the display area comprises notch display areas located at two sides of the notch and a regular display area, the regular display area comprises a plurality of first scan lines extending along a first direction, and each of the notch display areas comprises a plurality of second scan lines extending along the first direction;

the non-display areas at two opposite sides of the regular display area along the first direction are respectively a first non-display area and a second non-display area, the non-display areas at two opposite sides of each of the notch display areas along the first direction are respectively a third non-display area and a fourth non-display area, the third non-display area is at a side of the notch display area close to the first non-display area, and the fourth non-display area is at a side of the notch display area close to the second non-display area;

each of the first non-display area and the second non-display area is provided with first shift register units connected in cascade, each of the third non-display area and the fourth non-display area is provided with second shift register units connected in cascade, the first shift register units in the first non-display area are connected in cascade with the second shift register units in the third non-display area adjacent to the first non-display area, the second shift register units in adjacent third non-display areas are connected in cascade, the first shift register units in the second non-display area are connected in cascade with the second shift register units in the fourth non-display area adjacent to the second non-display area, and the second shift register units in adjacent fourth non-display areas are connected in cascade; and

each of the first shift register units comprises a first buffer unit, each of the second shift register units comprises a second buffer unit;

the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit;

or a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit;

or the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit, and a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit.

20. A touch display device comprising a touch display panel, the touch display panel comprising an array substrate, the array substrate comprising:

a display area; and

non-display areas surrounding the display area, wherein

at least one edge of the array substrate has i notch, i is an integer greater than or equal to 1;

the display area comprises notch display areas located at two sides of the notch and a regular display area, the regular display area comprises a plurality of first scan lines extending along a first direction, and each of the notch display areas comprises a plurality of second scan lines extending along the first direction;

the non-display areas at two opposite sides of the regular display area along the first direction are respectively a first non-display area and a second non-display area, the non-display areas at two opposite sides of each of the notch display areas along the first direction are respectively a third non-display area and a fourth non-display area, the third non-display area is at a side of the notch display area close to the first non-display area, and the fourth non-display area is at a side of the notch display area close to the second non-display area;

each of the first non-display area and the second non-display area is provided with first shift register units connected in cascade, each of the third non-display area and the fourth non-display area is provided with second shift register units connected in cascade, the first shift register units in the first non-display area are connected in cascade with the second shift register units in the third non-display area adjacent to the first non-display area, the second shift register units in adjacent third non-display areas are connected in cascade, the first shift register units in the second non-display area are connected in cascade with the second shift register units in the fourth non-display area adjacent to the second non-display area, and the second shift register units in adjacent fourth non-display areas are connected in cascade; and

each of the first shift register units comprises a first buffer unit, each of the second shift register units comprises a second buffer unit;

the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit;

or a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit;

or the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit, and a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit.