DECOUPLING CAPACITOR CIRCUIT

• US 20190081038A1
• Filed: 06/04/2018
• Published: 03/14/2019
• Est. Priority Date: 09/13/2017
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: KONG, Wan Chul
• Granted Patent: US 10,615,157 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

A decoupling capacitor includes a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library, a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library, a second PMOS transistor connected between the first NMOS transistor and the power rail, and a second NMOS transistor connected between the first PMOS transistor and the ground rail, wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor.

Claims

1. A decoupling capacitor, comprising:

a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library;

a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library;

a second PMOS transistor connected between the first NMOS transistor and the power rail; and

a second NMOS transistor connected between the first PMOS transistor and the ground rail,

wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor.

2. The decoupling capacitor of claim 1, wherein a source and a drain of the first PMOS transistor are connected to the power rail, along with an N-well region of the first PMOS transistor.

3. The decoupling capacitor of claim 1, wherein a source and a drain of the first NMOS transistor are connected to the ground rail, along with a bulk region of the first NMOS transistor.

4. The decoupling capacitor of claim 1, wherein a drain of the second PMOS transistor is connected to a gate of the first NMOS transistor, and a source of the second PMOS transistor is connected to the power rail.

5. The decoupling capacitor of claim 4, wherein a drain of the second NMOS transistor is connected to a gate of the first PMOS transistor, and a source of the second NMOS transistor is connected to the ground rail.

6. The decoupling capacitor of claim 5, wherein the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor have dimensions determined such that in response to a supply voltage being applied from the power rail, a voltage level at a gate of the second PMOS transistor has a level that is 40 to 60 percent of a voltage level of the supply voltage.

7. The decoupling capacitor of claim 1, wherein the first PMOS transistor and the second PMOS transistor are formed in a P-type active region.

8. The decoupling capacitor of claim 1, wherein the drain region of the first PMOS transistor is connected to the power rail by a metal wiring layer through a contact.

9. The decoupling capacitor of claim 1 where the first PMOS transistor and the second PMOS transistor share a first shared source region.

10. The decoupling capacitor of claim 9, where the first shared source region is connected to the power rail by a metal wiring layer through a contact.

11. The decoupling capacitor of claim 1, wherein the first NMOS transistor and the second NMOS transistor are formed in an N-type active region.

12. The decoupling capacitor of claim 1, wherein the drain region of the first NMOS transistor is connected to the ground rail by a metal wiring layer through a contact.

13. The decoupling capacitor of claim 1 where the first NMOS transistor and the second NMOS transistor share a second shared source region.

14. The decoupling capacitor of claim 13, where the second shared source region is connected to the ground rail by a metal wiring layer through a contact.