MOSFET WITH VERTICAL VARIATION OF GATE-PILLAR SEPARATION
First Claim
1. A trench Metal-Oxide-Semiconductor Field-effect Transistor (MOSFET) comprising:
- a semiconductor die including a substrate, an active device region formed upon the substrate, and an interconnection region formed upon the active device region, the active device region and the interconnection region separated by an interface surface;
a pair of trenches formed in the active device region, each of the pair of trenches extending from the interface surface to a dielectric trench bottom, the trenches laterally separated from one another by an intervening semiconductor pillar;
a conductive gate located within each of the trenches and separated, by a gate dielectric, from the intervening semiconductor pillar by a gate-pillar separation distance, wherein the gate-pillar separation distance decreases from a first depth location corresponding to the top of the conductive gate to a second depth location below the first depth location;
a conductive field plate located within each of the trenches, the conductive field plate located below the conductive gate and vertically separated from the conductive gate by an intervening dielectric, the conductive field plate laterally separated from the intervening semiconductor pillar by a dielectric material;
a source region in the intervening semiconductor pillar, the source region abutting each of the trenches;
a body region in the intervening semiconductor pillar, the body region abutting each of the trenches below the first depth location; and
a drift region in the semiconductor pillar contiguously extending from the body region to a drain region therebelow.
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Accused Products
Abstract
Apparatus and associated methods relate to a trench Metal-Oxide-Semiconductor Field-effect Transistor (MOSFET). The trench MOSFET includes a pair of longitudinal trenches formed in a semiconductor die, thereby forming an intervening longitudinal semiconductor pillar therebetween. Each of the pair of trenches has a field plates dielectrically isolated from a conductive gate. Each of the conductive gates is dielectrically isolated from the intervening semiconductor pillar via a gate dielectric. The thickness of the gate dielectric varies along a vertical dimension of the conductive gate, thereby providing a variation in a separation distance between each conductive gate and the intervening semiconductor pillar. The separation distance decreases from a gate/source overlap region to a channel inversion region. Such a varying separation distance can advantageously improve MOSFET operating parameters.
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Citations
29 Claims
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1. A trench Metal-Oxide-Semiconductor Field-effect Transistor (MOSFET) comprising:
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a semiconductor die including a substrate, an active device region formed upon the substrate, and an interconnection region formed upon the active device region, the active device region and the interconnection region separated by an interface surface; a pair of trenches formed in the active device region, each of the pair of trenches extending from the interface surface to a dielectric trench bottom, the trenches laterally separated from one another by an intervening semiconductor pillar; a conductive gate located within each of the trenches and separated, by a gate dielectric, from the intervening semiconductor pillar by a gate-pillar separation distance, wherein the gate-pillar separation distance decreases from a first depth location corresponding to the top of the conductive gate to a second depth location below the first depth location; a conductive field plate located within each of the trenches, the conductive field plate located below the conductive gate and vertically separated from the conductive gate by an intervening dielectric, the conductive field plate laterally separated from the intervening semiconductor pillar by a dielectric material; a source region in the intervening semiconductor pillar, the source region abutting each of the trenches; a body region in the intervening semiconductor pillar, the body region abutting each of the trenches below the first depth location; and a drift region in the semiconductor pillar contiguously extending from the body region to a drain region therebelow. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of manufacturing a trench-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the method comprising:
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etching two parallel trenches in a semiconductor die forming an intervening semiconductor pillar therebetween, the two trenches vertically extending from a top surface of the semiconductor die; oxidizing sidewalls and bottoms of the two trenches leaving a cavity within the oxidized sidewalls and the oxidized bottom of each of the two trenches; filling the cavities with polysilicon; etching the top portions of the polysilicon leaving polysilicon gates within the cavity; forming a source region in the semiconductor pillars; oxidizing the tops of the polysilicon gates and the sidewalls of the two trenches above the polysilicon gates, thereby tapering the sidewalls of the two trenches; and anisotropically etching the oxidization above the polysilicon gates exposing a laterally narrow portion of the top surface where a lateral width of the tapered profile of the intervening semiconductor pillar is smallest. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method for fabricating a trench gate MOSFET, the method comprising:
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etching a semiconductor die, thereby forming first trenches and a semiconductor pillar between adjacent pairs of the first trenches; forming a first insulation layer on a bottom and sidewalls of each of the first trenches and on a top surface of the semiconductor die; depositing a polysilicon layer on the top surface of the semiconductor die and in the first trenches; etching part of the polysilicon layer, thereby forming polysilicon gates in each of the trenches, a top surface of the polysilicon gate being lower than the top surface of the semiconductor die; forming a second insulation layer on the polysilicon gate, on a top portion of the sidewalls of the first trenches, and on the top surface of the semiconductor die; anisotropically etching part of the second insulation layer, thereby exposing a top part of each semiconductor pillar; forming a second trench in each exposed top part of the semiconductor pillars; and forming an electrode in each second trench. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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Specification