MOSFET WITH VERTICAL VARIATION OF GATE-PILLAR SEPARATION

• US 20190081147A1
• Filed: 09/13/2017
• Published: 03/14/2019
• Est. Priority Date: 09/13/2017
• Status: Abandoned Application

• Current Assignee: Polar Semiconductor, LLC (Sanken Electric Co., Ltd.), Sanken Electric Company Limited
• Original Assignee: Polar Semiconductor, LLC (Sanken Electric Co., Ltd.), Sanken Electric Company Limited
• Inventors: West, Peter, Dosev, Dosi, Rankila, Don, Kamimura, Tatsuya, Kosier, Steve
• Application Number:
  US15/703,699
• Publication Number:
  US 20190081147A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Apparatus and associated methods relate to a trench Metal-Oxide-Semiconductor Field-effect Transistor (MOSFET). The trench MOSFET includes a pair of longitudinal trenches formed in a semiconductor die, thereby forming an intervening longitudinal semiconductor pillar therebetween. Each of the pair of trenches has a field plates dielectrically isolated from a conductive gate. Each of the conductive gates is dielectrically isolated from the intervening semiconductor pillar via a gate dielectric. The thickness of the gate dielectric varies along a vertical dimension of the conductive gate, thereby providing a variation in a separation distance between each conductive gate and the intervening semiconductor pillar. The separation distance decreases from a gate/source overlap region to a channel inversion region. Such a varying separation distance can advantageously improve MOSFET operating parameters.

Claims

1. A trench Metal-Oxide-Semiconductor Field-effect Transistor (MOSFET) comprising:

a semiconductor die including a substrate, an active device region formed upon the substrate, and an interconnection region formed upon the active device region, the active device region and the interconnection region separated by an interface surface;

a pair of trenches formed in the active device region, each of the pair of trenches extending from the interface surface to a dielectric trench bottom, the trenches laterally separated from one another by an intervening semiconductor pillar;

a conductive gate located within each of the trenches and separated, by a gate dielectric, from the intervening semiconductor pillar by a gate-pillar separation distance, wherein the gate-pillar separation distance decreases from a first depth location corresponding to the top of the conductive gate to a second depth location below the first depth location;

a conductive field plate located within each of the trenches, the conductive field plate located below the conductive gate and vertically separated from the conductive gate by an intervening dielectric, the conductive field plate laterally separated from the intervening semiconductor pillar by a dielectric material;

a source region in the intervening semiconductor pillar, the source region abutting each of the trenches;

a body region in the intervening semiconductor pillar, the body region abutting each of the trenches below the first depth location; and

a drift region in the semiconductor pillar contiguously extending from the body region to a drain region therebelow.

2. The trench MOSFET of claim 1, wherein the gate-pillar separation distance is substantially constant from the second depth location to a third depth location below the second depth location.

3. The trench MOSFET of claim 2, wherein a lateral width of each of the pair of trenches continuously increases from the third depth location to the second depth location.

4. The trench MOSFET of claim 2, wherein a lateral width of the intervening semiconductor pillar continuously decreases from the third depth location to the second depth location.

5. The trench MOSFET of claim 2, wherein a lateral width of the intervening semiconductor pillar continuously decreases from the third depth location to the first depth location.

6. The trench MOSFET of claim 2, wherein a lateral width of the intervening semiconductor pillar continuously decreases from the third depth location to a top of the intervening semiconductor pillar.

7. The trench MOSFET of claim 1, wherein the intervening semiconductor pillar has a lateral dimension that is narrowest at a top of the intervening semiconductor pillar.

8. The trench MOSFET of claim 1, wherein a source/body contact is formed in an etched contact trench in the intervening semiconductor pillar from a top of the intervening semiconductor pillar to at least the first depth location corresponding to the top of the conductive gate.

9. The trench MOSFET of claim 8, wherein the source/body contact includes a metal contact made with the source region at a sidewall of the etched contact trench and a metal contact made with the body region at a bottom and a sidewall of the etched contact trench.

10. The trench MOSFET of claim 8, wherein a heavily doped body contact region is implanted into a bottom of the etched contact trench.

11. The trench MOSFET of claim 8, wherein the pair of trenches have dielectric sidewalls, and the dielectric sidewalls of the pair of trenches have a thickness at a depth location above the first depth location that is greater than the gate-pillar separation distance at the second depth location.

12. The trench MOSFET of claim 11, wherein the etched contact is self-aligned with the dielectric sidewalls of the pair of trenches, thereby centering the etched contact within the intervening semiconductor pillar.

13. The trench MOSFET of claim 1, wherein a ratio of a lateral width of each of the pair of trenches to a lateral width of the intervening semiconductor pillar is greater than one, as measured at the first depth location.

14. A method of manufacturing a trench-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the method comprising:

etching two parallel trenches in a semiconductor die forming an intervening semiconductor pillar therebetween, the two trenches vertically extending from a top surface of the semiconductor die;

oxidizing sidewalls and bottoms of the two trenches leaving a cavity within the oxidized sidewalls and the oxidized bottom of each of the two trenches;

filling the cavities with polysilicon;

etching the top portions of the polysilicon leaving polysilicon gates within the cavity;

forming a source region in the semiconductor pillars;

oxidizing the tops of the polysilicon gates and the sidewalls of the two trenches above the polysilicon gates, thereby tapering the sidewalls of the two trenches; and

anisotropically etching the oxidization above the polysilicon gates exposing a laterally narrow portion of the top surface where a lateral width of the tapered profile of the intervening semiconductor pillar is smallest.

15. The method of claim 14, further comprising:

anisotropically etching the exposed laterally narrow portion of the top surface of the semiconductor pillar, thereby exposing interior sidewalls and bottom of a contact trench within the intervening semiconductor pillar; and

forming a source contact on the exposed interior sidewalls of the contact trench.

16. The method of claim 15, further comprising:

forming a body contact on the exposed bottom of the contact trench.

17. The method claim 15, further comprising:

implanting, after anisotropically etching the exposed laterally narrow portion of the top surface of the semiconductor pillar, a body contact region into the contact trench.

18. The method claim 14, further comprising:

implanting, after oxidizing the tops of the polysilicon gates and the sidewalls above the polysilicon gates, a source region into the intervening semiconductor pillar.

19. The method of claim 14, wherein oxidizing sidewalls and the bottoms of the two longitudinal trenches leaving a cavity within the oxidized sidewalls and the oxidized bottom of each of the two longitudinal trenches comprises:

performing a sacrificial oxidation of the sidewalls and the bottoms of the two longitudinal trenches;

stripping the sacrificial oxide from the sidewalls and the bottoms of the two longitudinal trenches; and

performing a wet oxidation of the sidewalls and the bottoms of the two longitudinal trenches at a temperature greater than 1100°

C.

20. The method of claim 14, further comprising:

depositing, before filling top portions of the cavities with polysilicon, a dielectric above the polysilicon field plates within the trenches.

21. A method for fabricating a trench gate MOSFET, the method comprising:

etching a semiconductor die, thereby forming first trenches and a semiconductor pillar between adjacent pairs of the first trenches;

forming a first insulation layer on a bottom and sidewalls of each of the first trenches and on a top surface of the semiconductor die;

depositing a polysilicon layer on the top surface of the semiconductor die and in the first trenches;

etching part of the polysilicon layer, thereby forming polysilicon gates in each of the trenches, a top surface of the polysilicon gate being lower than the top surface of the semiconductor die;

forming a second insulation layer on the polysilicon gate, on a top portion of the sidewalls of the first trenches, and on the top surface of the semiconductor die;

anisotropically etching part of the second insulation layer, thereby exposing a top part of each semiconductor pillar;

forming a second trench in each exposed top part of the semiconductor pillars; and

forming an electrode in each second trench.

22. The method of claim 21, wherein forming a second insulation layer on the polysilicon gate, sidewalls of the first trenches, and the top surface of the semiconductor die creates tapered sidewalls of the first trenches, the method further comprising:

forming a source region of a first conductivity type extending from the surface of each semiconductor pillar; and

forming a body region of a second conductivity type below the source region and in each semiconductor pillar.

23. The method of claim 22, wherein a bottom of each of the second trenches is deeper than a bottom of each of the source regions.

24. The method of claim 22, wherein each of the semiconductor pillars laterally extends from each side of each of the second trenches, and wherein first trenches are separated from second trenches by the second insulation layer.

25. The method of claim 22, further comprising:

forming a first drift region of the first conductivity type below the body region and in each semiconductor pillar, a bottom of the first drift region is shallower than a bottom of the first trenches;

forming a second drift region of the first conductivity type below the first drift region and in each semiconductor pillar, a net impurity concentration of the second drift region less than a net impurity concentration of the first drift region; and

forming a drain region below the second drift region, a net impurity concentration of the drain region greater than the net impurity concentration of the second drift region.

26. The method of claim 25, further comprising:

forming an isolated polysilicon field plate below the polysilicon gate in each of the first trenches, wherein an interface between first and second drift regions is deeper than a top surface of the polysilicon field plate.

27. The method of claim 21, further comprising:

forming a third insulation layer that includes of BPSG on the second insulation layer before etching part of the second insulation layer.

28. The method of claim 21, wherein a thickness of the first insulation layer at the bottom of each of the first trenches is between two-thirds and one times a thickness of the first insulation layer at the sidewalls of the corresponding first trench.

29. The method of claim 21, wherein forming the first insulation layer on the bottom and the sidewalls of each of the first trenches and on the top surface of the semiconductor die comprises:

oxidizing the bottom and the sidewalls of each of the first trenches and the top surface of the semiconductor die using an oxidation temperature greater than 1000°

C.