DATA MANAGEMENT METHOD FOR MEMORY AND MEMORY APPARATUS

• US 20190087110A1
• Filed: 09/15/2017
• Published: 03/21/2019
• Est. Priority Date: 09/15/2017
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Li, Yung-Chun, Lin, Ping-Hsien, Chang, Yu-Ming
• Granted Patent: US 10,445,008 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.

Claims

1. A data management method for a memory, the memory including a plurality of memory pages, each of the memory pages including a plurality of memory cells, each of the memory cells including a first storage bit and a second storage bit, each of the memory cells having a first logical state, a second logical state, a third logical state, and a fourth logical state, the data management method comprising:

receiving, by a sanitizer, a data update command corresponding to a logical address, the logical address mapping to a physical address before receiving the data update command;

obtaining a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address; and

applying, by the sanitizer, a sanitizing voltage to the first target memory cell of the memory cells in the target memory page of the memory pages located at the physical address to change the logical state of the first target memory cell.

2. The data management method according to claim 1, wherein the step of applying the sanitizing voltage includes:

applying, by the sanitizer, a shot to change the logical state of the first target memory cell of the memory cells from the first logical state to the second logical state.

3. The method according to claim 2, wherein before the step of applying the shot, the step of applying the sanitizing voltage to the target memory block further includes:

applying, by the sanitizer, a first reading voltage to obtain the first target memory cell of the memory cells having the first logical state.

4. The data management method according to claim 1, wherein the step of applying the sanitizing voltage includes:

applying, by the sanitizer, a first reading voltage and a second reading voltage to obtain the first target memory cell of the memory cells having the second logical state; and

applying, by the sanitizer, a shot to change the logical state of the first target memory cell of the memory cells from the first logical state to the third logical state;

wherein the second reading voltage is greater than the first reading voltage.

5. The method according to claim 1, wherein the step of applying the sanitizing voltage includes:

applying, by the sanitizer, a second reading voltage and a third reading voltage to obtain the first target memory cell of the memory cells having the third logical state; and

applying, by the sanitizer, a shot to change the logical state of the first target memory cell of the memory cells from the third logical state to the fourth logical state;

wherein the third reading voltage is greater than the second reading voltage.

6. The method according to claim 1, wherein the step of applying the sanitizing voltage includes:

applying, by the sanitizer, a second reading voltage to obtain the first target memory cell of the memory cells having the first logical state and a second target memory cell of the memory cells having the second logical state; and

applying, by the sanitizer, a shot to change the logical state of the first target memory cell of the memory cells from the first logical state to the second logical state and the logical state of the second target memory cell of the memory cells from the second logical state to the third logical state.

7. The method according to claim 1, wherein the step of applying the sanitizing voltage includes:

applying, by the sanitizer, a third reading voltage to obtain the first target memory cell of the memory cells having the first logical state, a second target memory cell of the memory cells having the second logical state and a third target memory cell of the memory cells having the third logical state; and

applying, by the sanitizer, a shot to change the logical state of the first target memory cell of the memory cells from the first logical state to the second logical state, the logical state of the second target memory cell of the memory cells from the second logical state to the third logical state and the logical state of the third target memory cell of the memory cells from the third logical state to the fourth logical state.

8. The method according to claim 1, wherein the step of applying the sanitizing voltage includes:

applying, by the sanitizer, a first reading voltage to obtain the first target memory cell of the memory cells having the first logical state; and

applying a first programming voltage, by Incremental Step Pulse Programming (ISPP), to change the logical state of the first target memory cell of the memory cells from the first logical state to the fourth logical state.

9. The method according to claim 1, wherein the step of applying the sanitizing voltage includes:

applying, by the sanitizer, a first programming voltage, by Incremental Step Pulse Programming (ISPP), to change the logical state of the first target memory cell of the memory cells according to a data to be written.

10. A data management method for a memory, the memory including a plurality of memory pages, each of the memory pages including a plurality of memory cells, each of the memory cells including a first storage bit and a second storage bit, each of the memory cells having a first logical state, a second logical state, a third logical state, and a fourth logical state, the data management method comprising:

receiving, by a sanitizer, a data update command corresponding to a logical address, the logical address mapping to a physical address before receiving the data update command; and

wherein each of the memory cells further includes a third storage bit, each of the memory cells further has a fifth logical state, a sixth logical state, a seventh logical state, and an eighth logical state, the step of applying the sanitizing voltage includes;

applying, by the sanitizer, a first reading voltage and a second reading voltage to obtain the first target memory cell of the memory cells having the first logical state and a second target memory cell of the memory cells having the second logical state; and

applying, by the sanitizer, a second programming voltage, by full sequence programming, to change the logical state of the first target memory cell of the memory cells from the first logical state to the eighth logical state and the logical state of the second target memory cell of the memory cells from the second logical state to the seventh logical state;

wherein the second reading voltage is greater than the first reading voltage.

11. A memory apparatus, comprising:

a memory array, including a plurality of memory pages, each of the memory pages including a plurality of memory cells, each of the memory cells including a first storage bit and a second storage bit, each of the memory cells having a first logical state, a second logical state, a third logical state, and a fourth logical state; and

a sanitizer, for receiving a data update command corresponding to a logical address, the logical address mapping to a physical address before receiving the data update command to obtain a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address, and applying a sanitizing voltage to the first target memory cell of the memory cells in the target memory page of the memory pages located at the physical address to change the logical state of the first target memory cell.

12. The memory apparatus to claim 11, wherein the sanitizer applies a shot to change the logical state of the first target memory cell of the memory cells from the first logical state to the second logical state.

13. The memory apparatus to claim 12, wherein before the sanitizer applies the shot, the sanitizer applies a first reading voltage to obtain the first target memory cell of the memory cells having the first logical state.

14. The memory apparatus to claim 11, wherein the sanitizer applies a first reading voltage and a second reading voltage to obtain the first target memory cell of the memory cells having the second logical state, and applies a shot to change the logical state of the first target memory cell of the memory cells from the first logical state to the third logical state, wherein the second reading voltage is greater than the first reading voltage.

15. The memory apparatus to claim 11, wherein the sanitizer applies a second reading voltage and a third reading voltage to obtain the first target memory cell of the memory cells having the third logical state, and applies a shot to change the logical state of the first target memory cell of the memory cells from the third logical state to the fourth logical state, wherein the third reading voltage is greater than the second reading voltage.

16. The memory apparatus to claim 11, wherein the sanitizer applies a second reading voltage to obtain the first target memory cell of the memory cells having the first logical state and a second target memory cell of the memory cells having the second logical state, and applies a shot to change the logical state of the first target memory cell of the memory cells from the first logical state to the second logical state and the logical state of the second target memory cell of the memory cells from the second logical state to the third logical state.

17. The memory apparatus to claim 11, wherein the sanitizer applies a third reading voltage to obtain the first target memory cell of the memory cells having the first logical state, a second target memory cell of the memory cells having the second logical state and a third target memory cell of the memory cells having the third logical state, and applies a shot to change the logical state of the first target memory cell of the memory cells from the first logical state to the second logical state, the logical state of the second target memory cell of the memory cells from the second logical state to the third logical state and the logical state of the third target memory cell of the memory cells from the third logical state to the fourth logical state.

18. The memory apparatus to claim 11, wherein the sanitizer applies a first reading voltage to obtain the first target memory cell of the memory cells having the first logical state, and applies a first programming voltage, by Incremental Step Pulse Programming (ISPP), to change the logical state of the first target memory cell of the memory cells from the first logical state to the fourth logical state.

19. The memory apparatus to claim 11, wherein the sanitizer applies a first programming voltage, by Incremental Step Pulse Programming (ISPP), to change the logical state of the first target memory cell of the memory cells according to a data to be written.

20. A memory apparatus, comprising:

a memory array, including a plurality of memory pages, each of the memory pages including a plurality of memory cells, each of the memory cells including a first storage bit and a second storage bit, each of the memory cells having a first logical state, a second logical state, a third logical state, and a fourth logical state; and

a sanitizer, for receiving a data update command corresponding to a logical address, the logical address mapping to a physical address before receiving the data update command, and applying a sanitizing voltage to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address to change the logical state of the first target memory cell;

wherein each of the memory cells further includes a third storage bit, each of the memory cells further has a fifth logical state, a sixth logical state, a seventh logical state, and an eighth logical state, the sanitizer applies a first reading voltage and a second reading voltage to obtain the first target memory cell of the memory cells having the first logical state and a second target memory cell of the memory cells having the second logical state, and applies a second programming voltage, by full sequence programming, to change the logical state of the first target memory cell of the memory cells from the first logical state to the eighth logical state and the logical state of the second target memory cell of the memory cells from the second logical state to the seventh logical state, wherein the second reading voltage is greater than the first reading voltage.