MEMORY SYSTEM

• US 20190087121A1
• Filed: 02/27/2018
• Published: 03/21/2019
• Est. Priority Date: 09/20/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: KOBAYASHI, Hiroyuki, DEGUCHI, Jun, WADATSUMI, Junji, TOI, Takashi
• Granted Patent: US 10,838,655 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Claims

1. A memory system comprising:

first, second, third, and fourth memory, each of which is a nonvolatile memory;

a memory controller configured to modulate first write data for the first memory and second write data for the second memory into a first time slot of a data signal according to an allocation scheme, and modulate third write data for the third memory and fourth write data for the fourth memory into a second time slot of the data signal that is subsequent to the first time slot, according to the allocation scheme, wherein the allocation scheme defines in which of the first and second time slots the first to fourth write data for the first, second, third, and fourth memory are to be modulated, respectively;

a first bridge circuit configured to extract the first write data from the first time slot of the data signal according to the allocation scheme;

a second bridge circuit configured according to the allocation scheme to extract the second write data from the first time slot of the data signal;

a third bridge circuit configured according to the allocation scheme to extract the third write data from the second time slot of the data signal; and

a fourth bridge circuit configured according to the allocation scheme to extract the fourth write data from the second time slot of the data signal.

2. The memory system according to claim 1, wherein the allocation scheme also defines a format for modulating write data for two different memory into one time slot.

3. The memory system according to claim 2, wherein

the first bridge circuit extracts the first write data from the data signal transmitted by the memory controller,

the second bridge circuit extracts the second data from the data signal transmitted by the first bridge circuit,

the third bridge circuit extracts the third write data from the data signal transmitted by the second bridge circuit, and

the fourth bridge circuit extracts the fourth data from the data signal transmitted by the third bridge circuit.

4. The memory system according to claim 3, wherein each of the first, second, and third bridge circuits is configured to remove the corresponding first, second, and third write data from the data signal after extraction thereof.

5. The memory system according to claim 4, wherein each of the first, second, and third bridge circuits is configured to replace the removed write data with first, second, and third read data that is read from the first, second, and third memory, respectively.

6. The memory system according to claim 5, wherein the fourth bridge circuit is configured to replace the extracted fourth write data with fourth read data that is read from the fourth memory.

7. The memory system according to claim 6, wherein the controller is configured to transmit the data signal containing the first, second, third, and fourth write data to the first bridge circuit, and receive data signal containing the first, second, third, and fourth read data from the first bridge circuit.

8. The memory system according to claim 3, wherein each of the bridge circuits includes a clock and data recovery circuit configured to perform phase synchronization on the data signal against a synchronization signal.

9. The memory system according to claim 8, wherein the synchronization signal is embedded in the data signal.

10. The memory system according to claim 8, wherein the synchronization signal and the data signal are transmitted separately.

11. The memory system according to claim 8, wherein the clock and data recovery circuits (CDRs) of the each bridge circuit are each configured to correct a phase of the synchronization signal using bandwidths having different widths, the bandwidth for the CDR of the first bridge circuit being the narrowest and the bandwidth for the CDR of the fourth bridge circuit being the widest.

12. The memory system according to claim 1, wherein the controller is configured to transmit the data signal containing the first, second, third, and fourth write data to the first bridge circuit, and receive a different data signal containing first, second, third, and fourth read data that is read from the first, second, third, and fourth memory, respectively, from the first bridge circuit.

13. The memory system according to claim 12, wherein the first and second read data are modulated into a third time slot of the different data signal, and the third and fourth read data are modulated into a fourth time slot of the different data signal that is subsequent to the third time slot.

14. The memory system according to claim 13, wherein base data of the different data signal is transmitted from the fourth bridge circuit to the third bridge circuit, then from the third bridge circuit to the second bridge circuit, and then from the second bridge circuit to the first bridge circuit.

15. The memory system according to claim 13, wherein the base data of the different data signal contains only the fourth read data when transmitted from the fourth bridge circuit to the third bridge circuit, only the third and fourth read data when transmitted from the third bridge circuit to the second bridge circuit, and only the second, third, and fourth data when transmitted from the second bridge circuit to the first bridge circuit.

16. A memory system comprising:

a plurality of nonvolatile memory packages;

a plurality of circuits, each connected to and controlling read and write operations performed on one of the nonvolatile memory packages; and

a memory controller circuitry directly connected to at least one of the circuits and not all of the circuits and configured to modulate first write data to be written into one of the nonvolatile memory packages and second write data to be written into another one of the nonvolatile memory packages into multiple time slots of a data signal according to an allocation scheme,

wherein each of the circuits, upon receipt of the data signal, extracts write data to be written into the nonvolatile memory package connected thereto, according to the allocation scheme.

17. The memory system according to claim 16, wherein the plurality of circuits include a first circuit directly connected to the memory controller to receive the data signal from the memory controller, a second circuit directly connected to the first circuit to receive the data signal from the first circuit, a third circuit directly connected to the second circuit to receive the data signal from the second circuit, and a fourth circuit directly connected to the third circuit to receive the data signal from the third circuit.

18. The memory system according to claim 17, wherein the first circuit is also configured to transmit a different data signal containing read data from each of the nonvolatile memory packages to the memory controller.

19. The memory system according to claim 17, wherein the fourth circuit is directly connected to the memory controller to transmit the data signal to the memory controller.

20. The memory system according to claim 19, wherein the data signal transmitted from the fourth circuit to the memory controller contains read data from each of the nonvolatile memory packages.