METHODS AND APPARATUS TO PROVIDE USER-LEVEL ACCESS AUTHORIZATION FOR CLOUD-BASED FIELD-PROGRAMMABLE GATE ARRAYS
First Claim
1. An apparatus, comprising:
- a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory, the first memory storing a bitstream, the second memory storing a first user tag associated with the bitstream; and
a kernel having an FPGA driver operatively coupled to the FPGA, the FPGA driver to;
receive a command associated with accessing the FPGA from a user-executed application;
identify a second user tag associated with the command; and
determine whether the command is to be accepted based on the second user tag.
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Abstract
Methods and apparatus to provide user-level access authorization for cloud-based filed-programmable gate arrays are disclosed. An example apparatus includes a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory. The first memory stores a bitstream. The second memory stores a first user tag associated with the bitstream. The example apparatus further includes a kernel having an FPGA driver operatively coupled to the FPGA. The FPGA driver is to receive a command associated with accessing the FPGA from a user-executed application. The FPGA driver is further to identify a second user tag associated with the command. The FPGA driver is further to determine whether the command is to be accepted based on the second user tag.
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Citations
20 Claims
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1. An apparatus, comprising:
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a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory, the first memory storing a bitstream, the second memory storing a first user tag associated with the bitstream; and a kernel having an FPGA driver operatively coupled to the FPGA, the FPGA driver to; receive a command associated with accessing the FPGA from a user-executed application; identify a second user tag associated with the command; and determine whether the command is to be accepted based on the second user tag. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A non-transitory computer readable storage medium comprising instructions that, when executed, cause one or more processors to at least:
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load a bitstream into a first memory of a field-programmable gate array (FPGA); load a first user tag into a second memory of the FPGA different from the first memory, the first user tag being associated with the bitstream; identify a command associated with accessing the FPGA received from a user-executed application; identify a second user tag associated with the command; and determine whether the command is to be accepted based on the second user tag. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method, comprising:
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loading, by executing a computer readable instruction with one or more processors, a bitstream into a first memory of a field-programmable gate array (FPGA); loading, by executing a computer readable instruction with the one or more processors, a first user tag into a second memory of the FPGA different from the first memory, the first user tag being associated with the bitstream; receiving a command associated with accessing the FPGA from a user-executed application; identifying, by executing a computer readable instruction with the one or more processors, a second user tag associated with the command; and determining, by executing a computer readable instruction with the one or more processors, whether the command is to be accepted based on the second user tag. - View Dependent Claims (17, 18, 19, 20)
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Specification