High Frame Rate Display

• US 20190088208A1
• Filed: 08/31/2018
• Published: 03/21/2019
• Est. Priority Date: 09/21/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Chang, Ting-Kuo, Jamshidi Roudbari, Abbas, Tsai, Tsung-Ting, Rieutort-Louis, Warren S., Ono, Shinya, Yeh, Shin-Hung, Lee, Chien-Ya, Yang, Shyuan
• Granted Patent: US 10,984,727 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/021 Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
• CPC Class Codes: G09G 2310/0213 controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes

Abstract

A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

Claims

1. A display, comprising:

rows and columns of pixels;

gate lines that are configured to supply gate signals to the rows;

data lines including alternating odd and even data lines, wherein the data lines include pairs of data lines each including one of the odd data lines and an adjacent one of the even lines, wherein each column of the pixels includes a respective one of the pairs of the data lines;

demultiplexer circuitry coupled to the data lines; and

display driver circuitry coupled to the demultiplexer circuitry, wherein the demultiplexer circuitry is configured to provide the pixels of each column with data from the display driver circuitry using the pair of data lines for that column and wherein the demultiplexer circuitry is configured to operate alternately in;

a first mode in which the demultiplexer circuitry provides data from the display driver circuitry to the odd data lines while the display driver circuitry asserts a gate line in a first of the rows; and

a second mode in which the demultiplexer circuitry provides data from the display driver circuitry to the even lines while the display driver circuitry asserts a gate line in a second of the rows.

2. The display defined in claim 1, wherein the display driver circuitry is configured to supply the demultiplexer circuitry with first and second clock signals.

3. The display defined in claim 2, wherein the demultiplexer circuitry comprises a 1:

2 demultiplexer in each column.

4. The display defined in claim 3 wherein the 1:

2 demultiplexer in each column has an input and first and second outputs, wherein the first output is coupled to the odd data line of that column and the second output is coupled to the even data line of that column.

5. The display defined in claim 4 wherein each of the pixels includes a light-emitting diode.

6. The display defined in claim 5 wherein the pixels comprise thin-film transistors having gates controlled by the gate signals.

7. A display, comprising:

rows and columns of pixels;

gate lines that are configured to supply gate signals to the rows;

data lines including alternating odd and even data lines, wherein the data lines include pairs of data lines each including one of the odd data lines and an adjacent one of the even lines, wherein each column of the pixels includes a respective one of the pairs of the data lines;

demultiplexer circuitry coupled to the data lines; and

display driver circuitry coupled to the demultiplexer circuitry, wherein the demultiplexer circuitry is configured to provide the pixels of each column with data from the display driver circuitry using the pair of data lines for that column and wherein the demultiplexer circuitry and display driver circuitry are configured to operate in;

a first state in which the demultiplexer circuitry provides data from the display driver circuitry to the odd data lines and then leaves the odd data lines floating; and

a second state in which the demultiplexer circuitry provides data from the display driver circuitry to the even lines and then leaves the even data lines floating.

8. The display defined in claim 7 wherein the demultiplexer circuitry and the display driver circuitry are further configured to operate in a third state following the first and second states in which a given one of the gate signals on a given one of the gate lines is asserted to load data from the odd data lines into a first of the rows of pixels associated with the given one of the gate lines and to load data from the even data lines into a second of the rows of pixels associated with the given one of the gate lines.

9. The display defined in claim 8 wherein each of the pixels includes a light-emitting diode.

10. The display defined in claim 8, wherein the display driver circuitry is configured to supply the demultiplexer circuitry with first and second clock signals.

11. The display defined in claim 8, wherein the demultiplexer circuitry comprises a 1:

2 demultiplexer in each column.

12. The display defined in claim 11 wherein the 1:

2 demultiplexer in each column has an input and first and second outputs, wherein the first output is coupled to the odd data line of that column and the second output is coupled to the even data line of that column.

13. The display defined in claim 12 wherein the pixels comprise thin-film transistors having gates controlled by the gate signals.

14. A display, comprising:

rows and columns of pixels;

gate lines that are configured to supply gate signals to the rows;

data lines including alternating odd and even data lines, wherein the data lines include pairs of data lines each including one of the odd data lines and an adjacent one of the even lines, wherein each column of the pixels includes a respective one of the pairs of the data lines;

demultiplexer circuitry coupled to the data lines; and

display driver circuitry coupled to the demultiplexer circuitry, wherein the demultiplexer circuitry is configured to provide the pixels of each column with data from the display driver circuitry using the pair of data lines for that column and wherein the demultiplexer circuitry and display driver circuitry are configured to operate in;

a first mode in which the demultiplexer circuitry provides data from the display driver circuitry to the odd data lines; and

a second mode in which the demultiplexer circuitry provides data from the display driver circuitry to the even lines; and

a third mode in which the data on the odd data lines and even data lines is loaded into the pixels.

15. The display defined in claim 14 wherein the demultiplexer circuitry and display driver circuitry are configured to:

during the third mode, supply a given gate signal with a given one of the gate lines to load the data on the odd data lines and the even data lines into the pixels.

16. The display defined in claim 14 wherein a given one of the gate lines is associated with a first of the rows of pixels and a second of the rows of pixels, and wherein the demultiplexer circuitry and display driver circuitry are configured to:

during the third mode, supply a given gate signal with the given one of the gate lines to load the data on the odd data lines into the first of the rows of pixels and to load the data on the even data lines into the second of the rows of pixels.

17. The display defined in claim 16, wherein the demultiplexer circuitry comprises a 1:

2 demultiplexer in each column.

18. The display defined in claim 17 wherein each of the pixels includes a light-emitting diode.

19. The display defined in claim 18, wherein the display driver circuitry is configured to supply the demultiplexer circuitry with first and second clock signals.

20. The display defined in claim 17 wherein the 1:

2 demultiplexer in each column has an input and first and second outputs, wherein the first output is coupled to the odd data line of that column and the second output is coupled to the even data line of that column and wherein the pixels comprise thin-film transistors having gates controlled by the gate signals.