PACKAGED INTEGRATED CIRCUIT HAVING STACKED DIE AND METHOD FOR THEREFOR

• US 20190088576A1
• Filed: 03/19/2018
• Published: 03/21/2019
• Est. Priority Date: 09/19/2017
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: HIGGINS, III, LEO M., Brauchler, Fred T., Carpenter, Burton Jesse, Liu, Jinmei, Ching, JR., Mariano Layson, Yao, Jinzhong, Pang, Xingshou, Wang, Jianhong, Wei, Yadong
• Granted Patent: US 10,446,476 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/27334 using preformed layer
• CPC Class Codes: H01L 2224/27436 Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/278 Post-treatment of the layer connector
• CPC Class Codes: H01L 2224/27848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/29082 Two-layer arrangements
• CPC Class Codes: H01L 2224/29083 Three-layer arrangements
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/3201 Structure
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/3303 Layer connectors having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/33051 Layer connectors having different shapes
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73215 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83855 : Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/92147 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/42 : Wire connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H04L 25/0266 : Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.

Claims

1. A packaged integrated circuit (IC) device comprising:

a first IC die;

a first inductor in the first IC die;

a first layer of adhesive on a first major surface of the first IC die;

an isolation layer over the first layer of adhesive;

a second layer of adhesive on the isolation layer;

a second IC die on the second layer of adhesive;

a second inductor in the second IC die aligned to communicate with the first inductor,

wherein the isolation layer extends a prespecified distance beyond a first edge of the second IC die.

2. The IC device of claim 1 further comprising:

a conductive ring beneath the second layer of adhesive extending past the first edge of the second IC die, wherein the first edge is perpendicular to the second layer of adhesive and the conductive ring.

3. The IC device of claim 1 wherein:

at least one of the first and second adhesive layers is a die attach film.

4. The IC device of claim 1 further comprising:

a lead frame flag, wherein the first die is attached to the lead frame flag;

wire bonds between the first IC die and a first set of lead fingers; and

wire bonds between the second IC die and a second set of lead fingers.

5. The IC device of claim 1 wherein:

the isolation layer includes material that is one of a group consisting of a dielectric, epoxy, bismaleimide triazine (BT), FR-4, a resin, and a polyimide material.

6. The IC device of claim 1 wherein:

creepage distance between the first edge of the second IC die and a first edge of the insulator layer is at least 100 micrometers.

7. The IC device of claim 2 wherein:

minimum distance between the first edge of the second IC die and a perimeter of the conductive ring extending past the first edge of the second IC die is at least 10 micrometers.

8. The IC device of claim 1 wherein:

one of the first IC die and the second IC die is coupled to a high voltage supply and the other one of the first IC die and the second IC die is coupled to a low voltage supply.

11. The IC device of claim 2 further comprising:

corners of outer perimeter of the conductive ring are rounded.

12. The IC device of claim 2 wherein:

the conductive ring is made of copper and extends around all edges of the second IC die that are perpendicular to the second layer of adhesive and the conductive ring.

13. The IC device of claim 1 wherein:

thickness of the first adhesive layer, the second adhesive layer, and the isolation layer together is at least 5 micrometers.

14. The IC device of claim 1 wherein:

thickness of the first adhesive layer, the second adhesive layer, and the isolation layer together is between 90 and 500 micrometers.

9. A method of making a packaged integrated circuit (IC) device comprising:

attaching a bottom side of a first IC die to a flag of a lead frame, wherein the first IC die includes a first inductor;

attaching an isolation barrier to a top side of the first IC die with a first adhesive layer between the top side of the first IC die and a bottom side of the isolation barrier;

attaching a second IC die to a top side of the isolation barrier with a second adhesive layer between the top side of the isolation barrier and a bottom side of the second IC die, wherein

the second IC die includes a second inductor positioned to communicate signals to and from the first inductor, and

the isolation barrier extends beyond a first edge of the second die a distance sufficient to be greater than or equal to a specified creepage distance.

10. The method of claim 9 wherein:

thickness of the first adhesive layer, the second adhesive layer, and the isolation layer together is at least one of the group consisting of;

at least 5 micrometers and between 90 and 500 micrometers.

15. The method of claim 9 further comprising:

removing only a portion of a copper coating from the one side of the isolation barrier to leave a ring of conductive material on the that side of the isolation barrier, wherein an inner perimeter of the ring is outside a position of the first and second inductors and an outer perimeter of the ring is outside a perimeter of the second IC die.

16. The method of claim 9 further comprising:

forming wire bonds between contacts on the first IC die and a first set of lead fingers;

forming wire bonds between contacts on the second IC die and a second set of lead fingers; and

encapsulating the lead frame flag, first die, isolation layer, second die and wire bonds.

17. The method of claim 9 further comprising:

curing the first and second adhesive layers.

18. The method of claim 9 wherein:

at least one of the first and second adhesive layers are die attach film.

19. The method of claim 9 wherein:

the specified creepage distance is at least 100 micrometers.

20. The method of claim 15 wherein:

minimum distance between the first edge of the second IC die and a perimeter of the conductive ring extending past the first edge of the second IC die is at least 5 micrometers.