METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED GATES AND GATE EXTENSIONS AND THE RESULTING STRUCTURE

• US 20190088767A1
• Filed: 09/20/2017
• Published: 03/21/2019
• Est. Priority Date: 09/20/2017
• Status: Active Application

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Liebmann, Lars, Zang, Hui, Bentley, Steven
• Granted Patent: US 10,283,621 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.

Claims

1. A method comprising:

forming an opening that extends through a conformal sacrificial gate layer that covers a capped semiconductor fin, through the capped semiconductor fin and into a substrate, the sacrificial gate layer comprising a sacrificial material and the opening dividing the capped semiconductor fin into a pair of semiconductor fins having sacrificial fin caps;

forming, in the opening, an isolation region and a sacrificial region above the isolation region, the sacrificial region comprising the sacrificial material;

recessing the sacrificial material to form a recess, the recess extending laterally between adjacent ends of the semiconductor fins and further wrapping around upper portions of the semiconductor fins and the sacrificial fin caps on the semiconductor fins;

filling the recess with dielectric spacer material to form a spacer;

removing the sacrificial material; and

using the spacer as a mask to simultaneously form gates and a gate extension, the gates being positioned laterally adjacent to outer ends and opposing sides of the semiconductor fins and the gate extension being within a space that is above the isolation region and that extends laterally between and is in direct contact with the adjacent ends of the semiconductor fins and with the gates.

2. The method of claim 1, the sacrificial material and the spacer comprising different materials so that the sacrificial material can be selectively removed.

3. The method of claim 1,

the isolation region being formed in the substrate between lower source/drain regions, and

the method further comprising, after the filling of the recess and before the removing of the sacrificial material:

removing the sacrificial fin caps;

forming upper source/drain regions on the semiconductor fins; and

forming dielectric caps on the upper source/drain regions such that the spacer wraps around the upper source/drain regions and the dielectric caps.

4. The method of claim 3, the sacrificial fin caps and the spacer comprising different materials so that the sacrificial fin caps can be selectively removed.

5. The method of claim 1,

the removing of the sacrificial material creates a cavity below the spacer, the cavity extending laterally between the adjacent ends of the semiconductor fins and wrapping around the semiconductor fins, and

the method further comprising:

conformally depositing a gate dielectric layer;

depositing gate conductor material so as to fill the cavity; and

performing a selective anisotropic etch process using the spacer as the mask to remove portions of the gate dielectric layer and the gate conductor material outside the cavity such that, within the cavity below the spacer, the gate dielectric layer and the gate conductor material extends laterally between the adjacent ends of the semiconductor fins and also wraps around the semiconductor fins.

6. The method of claim 1, further comprising forming a gate contact extending through interlayer dielectric material and through the spacer to the gate extension.

7. The method of claim 1, further comprising forming an extension cut isolation region that extends through interlayer dielectric material, the spacer and the gate extension to the isolation region, the extension cut isolation region electrically isolating a first gate on a first side of the gate extension from a second gate on a second side of the gate extension.

8. A method comprising:

forming openings that extend through a conformal sacrificial gate layer that covers multiple capped semiconductor fins, each opening further extending through one of the capped semiconductor fins and into a substrate, the sacrificial gate layer comprising a sacrificial material and the openings dividing the capped semiconductor fins into pairs of semiconductor fins having sacrificial fin caps;

forming, in each opening, an isolation region and a sacrificial region above the isolation region, the sacrificial region comprising the sacrificial material;

recessing the sacrificial material to form recesses, each recess extending laterally between adjacent ends of semiconductor fins in a corresponding pair of semiconductor fins and further wrapping upper portions of the semiconductor fins in the corresponding pair and sacrificial fin caps on the semiconductor fins in the corresponding pair;

filling the recesses with dielectric spacer material to form spacers, respectively;

removing the sacrificial material;

using the spacers as masks during gate and gate extension formation such that each spacer is used to simultaneously form gates and a gate extensions, the gates being positioned laterally adjacent to outer ends and opposing sides of the semiconductor fins in the corresponding pair and the gate extension being within a space that is above the isolation region and that extends laterally between and is in direct contact with the adjacent ends of the semiconductor fins in the corresponding pair and with the gates; and

forming an extension cut isolation region that extends through interlayer dielectric material, through one of the spacers and through the gate extension between one of the pairs of semiconductor fins.

9. The method of claim 8, the sacrificial material and the spacers comprising different materials so that the sacrificial material can be selectively removed.

10. The method of claim 8,

the isolation region being formed in the substrate between lower source/drain regions, and

the method further comprising, after the filling of the recesses and before the removing of the sacrificial material:

removing all sacrificial fin caps;

forming upper source/drain regions all semiconductor fins of the pairs of semiconductor fins; and

forming dielectric caps all upper source/drain regions such that each spacer wraps around the upper source/drain regions on the semiconductor fins of the corresponding pair and further around the dielectric caps on the upper source/drain regions.

11. The method of claim 10, the sacrificial fin caps and the spacers comprising different materials so that the sacrificial fin caps can be selectively removed.

12. The method of claim 8,

the removing of the sacrificial material creates cavities below the spacers such that each cavity below each spacer extends laterally between the adjacent ends of the semiconductor fins in the corresponding pair and further wraps around the semiconductor fins in the corresponding pair, and

the method further comprising:

conformally depositing a gate dielectric layer;

depositing gate conductor material so as to fill the cavities; and

performing a selective anisotropic etch process using the spacers as masks to remove portions of the gate dielectric layer and the gate conductor material outside the cavities such that, within each cavity below each spacer, the gate dielectric layer and the gate conductor material extends laterally between the adjacent ends of the semiconductor fins of the corresponding pair and also wraps around the semiconductor fins of the corresponding pair.

13. The method of claim 8, further comprising forming gate contacts that extend through interlayer dielectric material and through the spacers to gate extensions.

14. An integrated circuit structure comprising:

a substrate; and

a pair of transistors on the substrate and comprising;

a pair of semiconductor fins, the semiconductor fins in the pair extending vertically between lower source/drain regions in the substrate and upper source/drain regions, respectively, and the semiconductor fins being in end-to-end alignment;

gates positioned laterally adjacent to outer ends and opposing sides of the semiconductor fins;

a gate extension above an isolation region and extending laterally between and in direct contact with adjacent ends of the semiconductor fins and with the gates; and

a spacer above the gate extension and further above the gates and wrapping around the upper source/drain regions.

15. The integrated circuit structure of claim 14, wherein sidewalls of the spacer are aligned vertically with sidewalls of the gates and the gate extension below.

16. The integrated circuit structure of claim 14, the isolation region being between the lower source/drain regions.

17. The integrated circuit structure of claim 14, further comprising a spacer layer on the substrate and electrically isolating the gates from the lower source/drain regions.

18. The integrated circuit structure of claim 14, further comprising a gate contact extending through interlayer dielectric material and the spacer to the gate extension.

19. The integrated circuit structure of claim 14, further comprising an extension cut isolation region extending through interlayer dielectric material, the spacer and the gate extension to the isolation region.

20. The integrated circuit structure of claim 14, further comprising a second pair of transistors on the substrate and parallel to the pair of transistors, wherein interlayer dielectric material electrically isolates second gates and a second gate extension of the second pair of transistors from the gates and the gate extension of the pair of transistors.