Low Power Clock Gating Circuit

• US 20190089354A1
• Filed: 09/20/2017
• Published: 03/21/2019
• Est. Priority Date: 09/20/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Venugopal, Vivekanandan, Seningen, Michael R., Bhatia, Ajay
• Granted Patent: US 10,461,747 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 5/134 with field-effect transistors

Abstract

A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.

Claims

1. A circuit comprising:

an input circuit configured to receive an enable signal;

clock enable circuitry configured to receive a clock signal;

a latch configured to capture and store an enabled state of the enable signal, wherein the enabled state corresponds to the enable signal being in an active state, wherein the latch comprises a feed forward circuit having a feed forward node and a feedback circuit having a feedback node, wherein the feedback circuit is coupled to provide a feedback signal to the feed forward circuit, wherein the feed forward circuit is configured to capture a current state of the enable signal when the clock signal is inactive, and wherein the feedback circuit is configured to cause the feed forward circuit to retain the enabled state of the enable signal when the clock signal transitions from a logic high state to a logic low state;

an output circuit configured to provide an output signal corresponding to a state of the clock signal when the latch is storing the enabled state;

wherein the circuit is configured such that dynamic power consumption does not change responsive to a change in the state of the clock signal when the latch is not storing the enabled state.

2. The circuit as recited in claim 1, wherein the input circuit is coupled to receive a test enable signal, and wherein the latch is further configured to capture and store the enabled state responsive to assertion of the test enable signal.

3. The circuit as recited in claim 2, wherein the latch is configured to cause the output circuit to hold the output signal at an inactive state, irrespective of a state of the clock signal, when neither of the enable and test enable signals are asserted.

5. The circuit as recited in claim 1, wherein the latch is configured to block transitions of the feed forward node when the clock signal is active.

7. The circuit as recited in claim 1, wherein, responsive to assertion of the enable signal, the feed forward circuit is configured to cause the feed forward node to be driven to the enabled state responsive to assertion of the enable signal and the clock signal entering the logic low state.

8. The circuit as recited in claim 1, wherein the feedback circuit is configured to provide a feedback signal on the feedback node in a state logically opposite that of a state of the feed forward node, wherein the feed forward circuit is configured to, when the clock signal is in the logic low state, set the state of the feed forward node based on the logically opposite state of the feedback signal.

9. The circuit as recited in claim 1, wherein the clock enable circuitry is configured to block transitions of the output signal when the clock signal is in the logic high state, irrespective of any transitions of the enable signal or any transitions of a test enable signal received by the input circuit.

10. The circuit as recited in claim 1, wherein the clock enable circuit is circuitry is configured to block transitions of the output signal when the enable signal and a test enable signal are both inactive.

4. (canceled)

6. (canceled)

11. A method comprising:

providing a clock signal to a clock gating circuit, the clock signal having an active state corresponding to a first logic level and an inactive state corresponding to a second logic level;

enabling the clock gating circuit responsive to assertion of an enable signal;

storing, in a latch, an enabled state of the enable signal, wherein storing the enabled state includes a feed forward circuit capturing the enabled state of the enable signal when the clock signal is inactive and a feedback circuit providing a feedback signal to the feed forward circuit to cause the feed forward circuit to retain the enabled state of the enable signal when the clock signal transitions from the active state to the inactive state;

providing an output signal corresponding to a current state of the clock signal when the clock gating circuit is enabled;

holding the output signal to a predetermined state, irrespective of a state of the clock signal, when the clock gating circuit is not enabled; and

inhibiting dynamic power consumption by the clock gating circuit due to state transitions of the clock signal when the clock gating circuit is not enabled.

12. The method as recited in claim 11, further comprising enabling the clock gating circuit responsive to at least one of the following:

receiving an enable signal in an asserted state when the clock signal is in the inactive state;

receiving a test enable signal in the asserted state when the clock signal is in the inactive state.

14. The method as recited in claim 11, further comprising clock enable circuitry in the clock gating circuit blocking transitions of the output signal, irrespective of transitions of the clock signal when the clock gating circuit is not enabled.

13. (canceled)

15. A clock gating circuit, comprising:

an input circuit configured to receive an enable signal;

clock enable circuitry configured to receive a clock signal, the clock signal having an active state corresponding to a first logic level and an inactive state corresponding to a second logic level;

a latch configured to capture and store, on a storage node, a state of the enable signal, wherein the latch is configured to capture a current state of the enable signal on the storage node when the clock signal is in an inactive state, and further configured to inhibit logical transitions of the storage node when the clock signal is in an active state, wherein the latch includes a feed forward circuit and a feedback circuit, wherein the feedback circuit includes an input coupled to the storage node and is coupled to provide a feedback signal to the feed forward circuit, wherein the feed forward circuit is configured to retain, responsive to the feedback signal, an asserted state of the enable signal on the storage node when the clock signal transitions to the inactive state; and

an output circuit configured to provide an output signal corresponding to a current state of the clock signal when the latch is storing the asserted state of the enable signal;

wherein the clock enable circuitry is configured to enable transitions of the output signal when the latch is storing the asserted state of the enable signal, and further configured to inhibit dynamic power consumption by the clock gating circuit, irrespective of transition by the clock signal, when the latch is not storing the asserted state of the enable signal.

17. The clock gating circuit as recited in claim 15, wherein the clock enable circuitry is configured to block transitions of the output signal when the clock signal is in an inactive state, irrespective of a state of the enable signal.

18. The clock gating circuit as recited in claim 15, wherein the clock enable circuitry is configured to block transitions of the output signal when the enable signal and a test enable signal are both inactive.

19. The clock gating circuit as recited in claim 15, wherein the input circuit is further configured to receive a test enable signal, wherein responsive to assertion of the test enable signal and the clock signal being in an inactive state, the latch is configured to capture and store, on the storage node, an asserted state of the test enable signal.

20. The clock gating circuit as recited in claim 19, wherein the clock enable circuitry is configured to allow transitions of the output signal, responsive to transitions of the clock signal, when the asserted state of the test enable signal is stored on the storage node.

16. (canceled)