Method of Mask Simulation Model for OPC and Mask Making

• US 20190094680A1
• Filed: 11/15/2017
• Published: 03/28/2019
• Est. Priority Date: 09/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Hsu-Ting, Chou, Chih-Shiang, Liu, Ru-Gun
• Granted Patent: US 10,495,967 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/78 by charged particle beam [CPB], e.g. electron beam patterning of masks
• CPC Class Codes: G03F 1/80 Etching
• CPC Class Codes: G03F 7/16 Coating processes; Apparatus therefor applying coatings to base materials in general B05; applying photosensitive compositions to base for photographic purposes G03C1/74
• CPC Class Codes: G03F 7/20 Exposure; Apparatus therefor photographic printing apparatus for making copies G03B27/00
• CPC Class Codes: G03F 7/26 Processing photosensitive materials; Apparatus therefor G03F7/12 - G03F7/24 take precedence
• CPC Class Codes: G03F 7/38 Treatment before imagewise removal, e.g. prebaking G03F7/265 takes precedence
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/0277 Electrolithographic processes
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes building a mask model to simulate a mask image and a compound lithography computational model to simulate a wafer pattern; calibrating the mask model using a measured mask image; calibrating the compound lithography computational model using a measured wafer data and the calibrated mask model; and performing an optical proximity correction (OPC) process to an IC pattern using the calibrated compound computational model, thereby generating a mask pattern for mask fabrication.

Claims

1. An integrated circuit (IC) method comprising:

building a mask model to simulate a mask image and a compound lithography computational (CLC) model to simulate a wafer pattern;

calibrating the mask model using a measured mask image;

calibrating the compound lithography computational model using a measured wafer data and the calibrated mask model; and

performing an optical proximity correction (OPC) process to an IC pattern using the calibrated compound computational model, thereby generating a mask pattern for mask fabrication.

2. The IC method of claim 1, further comprising making a mask based on the mask pattern.

3. The IC method of claim 2, further comprising performing a lithography process to a wafer using the mask.

4. The IC method of claim 3, wherein

the making of the mask includes coating a first resist layer to the mask, performing an electron-beam writing process according to the mask pattern to the first resist layer, and etching the mask through the patterned first resist layer;

and

the performing of the lithography process to the wafer includes coating a second resist layer to the wafer, and exposing the second resist layer using the mask to form a pattern second resist layer on the wafer.

5. The IC method of claim 1, further comprising

measuring a mask image before the calibrating of the mask model;

and

measuring a wafer pattern before the calibrating of the compound lithography computational model.

6. The IC method of claim 1, further comprising:

receiving the IC design layout including the IC pattern; and

forming a wafer target based on the IC pattern before the performing of the OPC process to the IC pattern.

7. The method of claim 6, wherein the performing of the OPC process includes

modifying the IC pattern;

simulating the IC pattern using the compound lithography computational model to generate a wafer contour of the IC pattern; and

determining a difference between the wafer contour and the wafer target.

8. The IC method of claim 7, further comprising repeating the modifying of the IC pattern and the simulating of the IC pattern if the difference is beyond a tolerable range.

9. The IC method of claim 8, wherein

the mask model is defined by a first formula to generate a mask image according to the IC pattern;

and

the compound lithography computational model is defined by a second formula to generate a wafer contour according to the mask model and a resist model.

10. An integrated circuit (IC) method comprising:

calibrating a mask model using a measured mask image;

calibrating a compound lithography computational model using a measured wafer data and the calibrated mask model; and

performing an optical proximity correction (OPC) process to an IC pattern using the calibrated compound computational model, thereby generating a mask pattern for mask fabrication.

11. The IC method of claim 10, further comprising:

receiving an IC design layout including the IC pattern; and

forming a wafer target based on the IC pattern before the performing of the OPC process to the IC pattern.

12. The method of claim 11, wherein the performing of the OPC process includes

modifying the IC pattern;

simulating the IC pattern using the compound lithography computational (CLC) model to generating a wafer contour of the IC pattern;

determining a difference between the wafer contour and the wafer target; and

repeating above steps if the difference is beyond a tolerable range.

13. The IC method of claim 12, wherein

the mask model is defined in a formula I(x, mp), wherein mp is a set of mask model parameters, and I(x, mp) is a mask image function that simulates an image of a pattern of a mask onto a semiconductor wafer during a lithography exposing process;

and

the CLC model is defined in a formula W(x)=Φ

₂(Φ

₁(I(x, mp))), wherein

W(x) defines a simulated wafer contour;

Φ

₁ defines a resist pattern function that simulates characteristics of a photoresist coated on the semiconductor wafer; and

Φ

₂ defines a wafer pattern function that simulates characteristics of an etching process applied to the semiconductor wafer.

14. The IC method of claim 10, further comprising making a mask based on the mask pattern.

15. The IC method of claim 14, further comprising performing a lithography process to a wafer using the mask.

16. The IC method of claim 15, further comprising

constructing the mask model to simulate a mask image and a compound lithography computational model to simulate a wafer contour;

measuring a mask image before the calibrating of the mask model; and

measuring a wafer pattern before the calibrating of the compound lithography computational model.

17. The method of claim 14, further comprising performing a fracturing process to the mask pattern, thereby generating an electron-beam shot map to be used in an electron-beam lithography process to pattern the mask.

18. The method of claim 17, further comprising performing a mask making process to the mask using the electron-beam shot map, wherein the mask making process includes the electron-beam lithography process.

19. An integrated circuit (IC) design system, comprising

a mask data module designed to collect mask imaging data;

a wafer data module designed to collect wafer manufacturing data from a wafer making process;

a first calibration module designed to calibrate a mask model based on the mask imaging data;

a second calibration module designed to calibrate a compound lithography computational model based on the wafer manufacturing data; and

an optical proximity correction (OPC) module designed to perform an OPC process using the mask model and the compound lithography computational mode.

20. The IC design system of claim 19, further comprising a model builder designed to build the mask model and the compound lithography computational model.