PROCESSORS, METHODS, AND SYSTEMS FOR A MEMORY FENCE IN A CONFIGURABLE SPATIAL ACCELERATOR

• US 20190095369A1
• Filed: 09/28/2017
• Published: 03/28/2019
• Est. Priority Date: 09/28/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fleming, Kermin, Glossop, Kent D., Steely, JR., Simon C.
• Granted Patent: US 10,496,574 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

Systems, methods, and apparatuses relating to a memory fence mechanism in a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a plurality of operations, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The processor also includes a fence manager to manage a memory fence between a first operation and a second operation of the plurality of operations.

Claims

1. A processor comprising:

a plurality of processing elements;

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as one of a plurality of dataflow operators in the plurality of processing elements, and the plurality of processing elements are to perform a plurality of operations, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements; and

a fence manager to manage a memory fence between a first operation and a second operation of the plurality of operations.

2. The processor of claim 1, further comprising a plurality of request address file (RAF) circuits including a first RAF circuit to request the memory fence by sending a fence-request message to the fence manager.

3. The processor of claim 2, wherein, in response to the fence-request message, the fence manager is to send a fence-open message to the plurality of RAF circuits to open the fence operation.

4. The processor of claim 3, wherein, in response to the fence-open message, each of the plurality of RAF circuits is to complete outstanding memory operations and send a fence-acknowledge message to the fence manager.

5. The processor of claim 4, further comprising a plurality of cache banks and wherein, in response to the fence-acknowledge message from each of the plurality of RAF circuits, the fence manager is to send a fence-open message to each of the plurality of cache banks.

6. The processor of claim 5, wherein, in response to the fence-open message, each of a plurality of cache banks is to complete outstanding memory operations and send a fence-acknowledge message to the fence manager.

7. The processor of claim 6, wherein, in response to the fence-acknowledge message from each of the plurality of cache banks, the fence manager is to send a fence-close message to each of a plurality of RAF circuits.

8. The processor of claim 7, further comprising an accelerator cache interconnect (ACI) to connect the plurality of RAF circuits to the plurality of cache banks

9. The processor of claim 8, wherein the ACI is to carry the fence-open message from the fence manager to the plurality of RAF circuits and the plurality of cache banks.

10. The processor of claim 1, wherein the fence manager includes a state machine.

11. The processor of claim 1, wherein the fence manager is also to buffer fence requests.

12. A method comprising:

receiving an input of a dataflow graph comprising a plurality of nodes;

overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements;

performing a plurality of operations of the dataflow graph with the interconnect network and the plurality of processing elements, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements; and

performing a fence operation to establish a memory fence between a first operation and a second operation of the plurality of operations.

13. The method of claim 12, further comprising, by a first request address file (RAF) circuit of a plurality of RAF circuits, requesting the memory fence by sending a fence-request message to a fence manager.

14. The method of claim 13, further comprising, by the fence manager in response to the fence-request message, sending a fence-open message to the plurality of RAF circuits to open the fence operation.

15. The method of claim 14, further comprising, by each of the plurality of RAF circuits is response to the fence-open message, completing outstanding memory operations and sending a fence-acknowledge message to the fence manager.

16. The method of claim 15, further comprising, by the fence manager in response to the fence-acknowledge message from each of the plurality of RAF circuits, sending a fence-open message to each of a plurality of cache banks.

17. The method of claim 16, further comprising, by each of the plurality of cache banks in response to the fence-open message, completing outstanding memory operations and sending a fence-acknowledge message to the fence manager.

18. The method of claim 17, further comprising, by the fence manager in response to the fence-acknowledge message from each of the plurality of cache banks, sending a fence-close message to each of a plurality of RAF circuits.

19. A system comprising:

a system memory; and

a processor including;

a plurality of processing elements;

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as one of a plurality of dataflow operators in the plurality of processing elements, and the plurality of processing elements are to perform a plurality of operations, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements; and

a fence manager to manage a memory fence between a first operation and a second operation of the plurality of operations, wherein the first operation and the second operation are to access the system memory.

20. The system of claim 19, wherein the processor also includes a plurality of request address file (RAF) circuits and a plurality of cache banks, and the fence manager is to cause each of the plurality of RAF circuits and each of the plurality cache banks to retire outstanding memory operations to the system memory.