APPARATUSES AND METHODS FOR TSV RESISTANCE AND SHORT MEASUREMENT IN A STACKED DEVICE
First Claim
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1. An apparatus comprising:
- a chip comprising;
a semiconductor substrate including a first surface and a second surface opposite to the first surface;
a first terminal formed above the first surface;
a second terminal formed above the second surface;
a buffer circuit coupled between the first and second terminals;
a first through-substrate via (TSV) penetrating the semiconductor substrate; and
a first switch coupled between the first terminal and the first TSV.
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Abstract
Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.
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Citations
20 Claims
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1. An apparatus comprising:
a chip comprising; a semiconductor substrate including a first surface and a second surface opposite to the first surface; a first terminal formed above the first surface; a second terminal formed above the second surface; a buffer circuit coupled between the first and second terminals; a first through-substrate via (TSV) penetrating the semiconductor substrate; and a first switch coupled between the first terminal and the first TSV. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus comprising:
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first, second, third and fourth chips stacked in this order, each of the first, second, third and fourth chips including first, second, third and fourth terminals formed above a first surface thereof, a memory cell array, and a buffer circuit; wherein each of the first, second and third chips includes fifth, sixth, seventh and eighth terminals formed above a second surface opposite to the first surface, the buffer circuit coupled in series between the first terminal and the eighth terminal, the second terminal coupled to the fifth terminal, the third terminal coupled to the sixth terminal and the fourth terminal coupled to the seventh terminal, and wherein each of the first, second and third chips includes first, second, third and fourth through-substrate vias (TSVs), each of the first to fourth TSVs penetrates a substrate; and a control circuit configured to be able to connect the first terminal to at least one of the first and second TSVs and further configured to be able to connect the eighth terminal to at least one of the third and fourth TSVs. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method comprising:
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providing a force signal from a force signal driver circuit to a first terminal of a first chip of a stacked semiconductor device via a first switch on the chip; coupling a sense circuit to the first terminal via a second switch on the chip to provide a sense signal; coupling the sense circuit to a second terminal on a second chip of the stacked semiconductor device to provide a sense feedback signal; sensing impedance between the first terminal and the second terminal based on the sense signal and the sense feedback signal. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification