GROUND LAYER DESIGN IN A PRINTED CIRCUIT BOARD (PCB)

• US 20190097313A1
• Filed: 09/22/2017
• Published: 03/28/2019
• Est. Priority Date: 09/22/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lee, JaeJin, Han, Dong-Ho, Hsu, Hao-Han
• Granted Patent: US 10,454,163 B2
• Time in Patent Office: Days
• CPC Class Codes: H01Q 1/242 specially adapted for hand-held use
• CPC Class Codes: H01Q 1/273 Adaptation for carrying or wearing by persons or animals
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 1/48 Earthing means; Earth screens; Counterpoises
• CPC Class Codes: H01Q 1/52 Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure absorbing means H01Q17/00
• CPC Class Codes: H05K 1/0225 Single or multiple openings in a shielding, ground or power plane H05K1/0227 takes precedence
• CPC Class Codes: H05K 2201/09681 Mesh conductors, e.g. as a ground plane
• CPC Class Codes: H05K 2201/10098 Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

Embodiments include apparatuses, methods, and systems including an electronic apparatus including an inductor within a circuit package affixed to a printed circuit board (PCB) having a ground layer, where the ground layer includes a mesh area that is substantially void along a contour of the inductor. An electronic apparatus may include a circuit package with an inductor, and a PCB, where the circuit package may be affixed to the PCB. The PCB may have a plurality of layers including a ground layer and a power layer, where the ground layer may be between the power layer and the inductor. The ground layer may include a mesh area that may be substantially void along a contour of the inductor within the circuit package. Other embodiments may also be described and claimed.

Claims

1. An electronic apparatus, comprising:

a circuit package with an inductor;

a printed circuit board (PCB), wherein the circuit package is affixed to the PCB, the PCB has a plurality of layers including a ground layer and a power layer, and wherein the ground layer is between the power layer and the inductor, the ground layer includes a mesh area that is substantially void along a contour of the inductor.

2. The electronic apparatus of claim 1, wherein the ground layer includes a conductive metal or an alloy of metal.

3. The electronic apparatus of claim 1, wherein the ground layer is a top metal layer of the PCB that is closest to the inductor.

4. The electronic apparatus of claim 1, wherein the PCB further includes a signal layer located at a same side of the ground layer as the power layer is located.

5. The computing device of claim 1, wherein the PCB is of a circular shape, a square, a rectangular shape, an elliptical shape, or a polygon shape.

6. The electronic apparatus of claim 1, wherein the circuit package comprises one of:

a chip scale package (CSP), a wafer-level package (WLP), a quad-flat no-leads (QFN) package, a dual-flat no-leads (DFN) package, or a package with overmold mounted on the PCB.

7. The electronic apparatus of claim 1, wherein the inductor includes a first coil segment and a second coil segment disjoint from the first coil segment, and the ground layer includes a first mesh area and a second mesh area, and wherein the first mesh area is substantially void along a contour of the first coil segment, and the second mesh area is substantially void along a contour of the second coil segment.

8. The electronic apparatus of claim 1, wherein the inductor is a spiral inductor.

9. The electronic apparatus of claim 1, wherein the inductor is an air core inductor (ACI).

10. The electronic apparatus of claim 1, wherein the inductor is a component in a fully integrated voltage regulator (FIVR) or a multi-chip integrated voltage regulator (McIVR).

11. The electronic apparatus of claim 1, wherein the electronic apparatus comprises a wearable device, a smartphone, or an Internet of Things (TOT) device, and the inductor is a component in an integrated voltage regulator (IVR) on a system-on-chip (SoC).

12. A printed circuit board (PCB), comprising:

a substrate; and

a ground layer on the substrate, wherein the ground layer includes a void area, wherein the void area is disposed at a location that substantially overlaps along a contour of an inductor within a circuit package, when the circuit package is affixed to the PCB.

13. The PCB of claim 12, wherein the ground layer includes a conductive metal or an alloy of metal.

14. The PCB of claim 12, wherein the ground layer is a top metal layer of the PCB that is closest to the inductor.

15. The PCB of claim 12, further comprising:

a power layer below the ground layer, or a signal layer below the ground layer.

16. The PCB of claim 12, wherein the circuit package comprises one of:

a chip scale package (CSP), a wafer-level package (WLP), a quad-flat no-leads (QFN) package, a dual-flat no-leads (DFN) package, or a package with overmold mounted on the PCB.

17. The PCB of claim 12, wherein the inductor includes a first coil segment and a second coil segment disjoint from the first coil segment, and the ground layer includes a first void area and a second void area, and wherein the first void area substantially overlaps along a contour of the first coil segment, and the second void area substantially overlaps along a contour of the second coil segment.

18. A computing device, comprising:

a processor;

a display coupled to the processor,

a circuit package with an inductor; and

a printed circuit board (PCB), wherein the circuit package is affixed to the PCB, the PCB has a plurality of layers including a ground layer and a power layer, and wherein the ground layer is between the power layer and the inductor, the ground layer includes a mesh area that is substantially void along a contour of the inductor.

19. The computing device of claim 18, wherein the ground layer includes a conductive metal or an alloy of metal.

20. The computing device of claim 18, wherein the ground layer is a top metal layer of the PCB that is closest to the inductor.

21. The computing device of claim 18, wherein the circuit package comprises one of:

a chip scale package (CSP), a wafer-level package (WLP), a quad-flat no-leads (QFN) package, a dual-flat no-leads (DFN) package, or a package with overmold mounted on the PCB.

22. The computing device of claim 18, wherein the inductor includes a first coil segment and a second coil segment disjoint from the first coil segment, and the ground layer includes a first mesh area and a second mesh area, and wherein the first mesh area is substantially void along a contour of the first coil segment, and the second mesh area is substantially void along a contour of the second coil segment.

23. The computing device of claim 18, wherein the inductor is an air core inductor (ACI).

24. The computing device of claim 18, wherein the inductor is a component in a fully integrated voltage regulator (FIVR) or a multi-chip integrated voltage regulator (McIVR).

25. The computing device of claim 18, wherein the computing device is a wearable device, a smartphone, or an Internet of Things (TOT) device, and the inductor is a component in an integrated voltage regulator (IVR) on a system-on-chip (SoC).