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PROCESSORS AND METHODS FOR CONFIGURABLE CLOCK GATING IN A SPATIAL ARRAY

  • US 20190101952A1
  • Filed: 09/30/2017
  • Published: 04/04/2019
  • Est. Priority Date: 09/30/2017
  • Status: Abandoned Application
First Claim
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1. A processor comprising:

  • a plurality of processing elements;

    an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and

    a configuration controller coupled to the plurality of processing elements to configure the plurality of processing elements according to configuration information for the dataflow graph, and clock gate at least one clocked component of a processing element based on the configuration information.

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