PROCESSORS AND METHODS FOR CONFIGURABLE CLOCK GATING IN A SPATIAL ARRAY

• US 20190101952A1
• Filed: 09/30/2017
• Published: 04/04/2019
• Est. Priority Date: 09/30/2017
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: DIAMOND, MITCHELL, KEEN, BENJAMIN, FLEMING, JR., KERMIN E.
• Application Number:
  US15/721,816
• Publication Number:
  US 20190101952A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/825 Dataflow computers
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatuses relating to configurable clock gating in spatial arrays are described. In one embodiment, a processor includes processing elements; an interconnect network between the processing elements; and a configuration controller, coupled to a first processing element and a second processing element of the plurality of processing elements and the first processing element having an output coupled to an input of the second processing element, to configure the second processing element to clock gate at least one clocked component of the second processing element, and configure the first processing element to send a reenable signal on the interconnect network to the second processing element to reenable the at least one clocked component of the second processing element when data is to be sent from the first processing element to the second processing element.

Claims

1. A processor comprising:

a plurality of processing elements;

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and

a configuration controller coupled to the plurality of processing elements to configure the plurality of processing elements according to configuration information for the dataflow graph, and clock gate at least one clocked component of a processing element based on the configuration information.

2. The processor of claim 1, wherein the at least one clocked component is an input buffer of multiple parallel input buffers within the processing element.

3. The processor of claim 1, wherein the at least one clocked component is an output buffer of multiple parallel input buffers within the processing element.

4. The processor of claim 1, wherein the at least one clocked component is an operation configuration register within the processing element to store an operation configuration of the configuration information.

5. The processor of claim 1, wherein the configuration controller is to clock gate at least one clocked component of a second processing element based on the configuration information.

6. The processor of claim 1, wherein the at least one clocked component comprises multiple parallel input buffers within the processing element, multiple parallel output buffers within the processing element, and an operation configuration register within the processing element to store an operation configuration of the configuration information, and the configuration controller is to independently clock gate each of those clocked components.

7. A method comprising:

configuring, with a configuration controller of a processor, a plurality of processing elements of the processor according to configuration information for a dataflow graph, wherein the processor comprises the plurality of processing elements and an interconnect network between the plurality of processing elements, and has the dataflow graph comprising a plurality of nodes overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements;

clock gating, with the configuration controller of the processor, at least one clocked component of a processing element based on the configuration information for the dataflow graph; and

performing an operation of the dataflow graph with the interconnect network and the plurality of processing elements when an incoming operand set arrives at the plurality of processing elements.

8. The method of claim 7, wherein the clock gating comprises clock gating an input buffer of multiple parallel input buffers within the processing element.

9. The method of claim 7, wherein the clock gating comprises clock gating an output buffer of multiple parallel input buffers within the processing element.

10. The method of claim 7, wherein the clock gating comprises clock gating an operation configuration register within the processing element to store an operation configuration of the configuration information.

11. The method of claim 7, wherein the clock gating comprises clock gating at least one clocked component of a second processing element based on the configuration information.

12. The method of claim 7, wherein the at least one clocked component comprises multiple parallel input buffers within the processing element, multiple parallel output buffers within the processing element, and an operation configuration register within the processing element to store an operation configuration of the configuration information, and the configuration controller is independently clock gating each of those clocked components.

13. A processor comprising:

a plurality of processing elements;

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and

a configuration controller, coupled to a first processing element and a second processing element of the plurality of processing elements and the first processing element having an output coupled to an input of the second processing element, to configure the second processing element to clock gate at least one clocked component of the second processing element, and configure the first processing element to send a reenable signal on the interconnect network to the second processing element to reenable the at least one clocked component of the second processing element when data is to be sent from the first processing element to the second processing element.

14. The processor of claim 13, wherein the configuration controller is to configure the first processing element to send the reenable signal and the data from the first processing element to the second processing element within a same clock cycle.

15. The processor of claim 13, wherein the at least one clocked component of the second processing element comprises multiple parallel input buffers within the second processing element.

16. The processor of claim 15, wherein the configuration controller is to configure the first processing element to clock gate multiple parallel output buffers within the first processing element, and reenable the multiple parallel output buffers when the data is to be sent from the multiple parallel output buffers within the first processing element to the multiple parallel input buffers within the second processing element.

17. The processor of claim 13, wherein the configuration controller, coupled to a third processing element of the plurality of processing elements and the first processing element having an output coupled to an input of the third processing element, to configure the third processing element to not clock gate any clocked component of the third processing element.

18. The processor of claim 17, wherein the configuration controller is to configure the third processing element to not clock gate any clocked component of the third processing element when a distance on the interconnect network between the first processing element and the third processing element is greater than a threshold distance to communicate within a same clock cycle between the first processing element and the third processing element.

19. A method comprising:

configuring, with a configuration controller of a processor coupled to a first processing element and a second processing element of a plurality of processing elements and the first processing element having an output coupled to an input of the second processing element, the second processing element to clock gate at least one clocked component of the second processing element, wherein the processor comprises the plurality of processing elements and an interconnect network between the plurality of processing elements, and has a dataflow graph comprising a plurality of nodes overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements;

configuring, with the configuration controller, the first processing element to send a reenable signal on the interconnect network to the second processing element to reenable the at least one clocked component of the second processing element when data is to be sent from the first processing element to the second processing element;

clock gating, with the configuration controller of the processor, the at least one clocked component of the second processing element;

sending, with the first processing element, a reenable signal on the interconnect network to the second processing element to reenable the at least one clocked component of the second processing element when the data is sent from the first processing element to the second processing element; and

performing an operation of the dataflow graph with the second processing element when an incoming operand set including the data arrives at the second processing element.

20. The method of claim 19, wherein the configuring of the first processing element causes the first processing element to send the reenable signal and the data from the first processing element to the second processing element within a same clock cycle.

21. The method of claim 19, wherein the clock gating comprises clock gating multiple parallel input buffers within the second processing element.

22. The method of claim 21, wherein the configuring of the first processing element causes the first processing element to clock gate multiple parallel output buffers within the first processing element, and reenable the multiple parallel output buffers when the data is sent from the multiple parallel output buffers within the first processing element to the multiple parallel input buffers within the second processing element.

23. The method of claim 19, further comprising configuring, with the configuration controller coupled to a third processing element of the plurality of processing elements and the first processing element having an output coupled to an input of the third processing element, the third processing element to not clock gate any clocked component of the third processing element.

24. The method of claim 23, wherein the configuring of the third processing element to not clock gate any clocked component of the third processing element is based on a distance on the interconnect network between the first processing element and the third processing element being greater than a threshold distance to communicate within a same clock cycle between the first processing element and the third processing element.