Converting a Stream of Data Using a Lookaside Buffer

• US 20190102178A1
• Filed: 11/30/2018
• Published: 04/04/2019
• Est. Priority Date: 07/15/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Zbiciak, Joseph Raymond Michael
• Granted Patent: US 10,649,775 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2205/067 Bidirectional FIFO, i.e. system allowing data transfer in two directions
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/654 Look-ahead translation
• CPC Class Codes: G06F 2212/681 Multi-level TLB, e.g. microTLB and main TLB
• CPC Class Codes: G06F 2212/684 TLB miss handling
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30098 : Register arrangements
• CPC Class Codes: G06F 9/30112 : comprising data of variable length
• CPC Class Codes: G06F 9/30145 : Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 : Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/32 : Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/345 : of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3822 : Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3867 : using instruction pipelines

Abstract

A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

Claims

1. A method of converting a stream of data, the method comprising:

preloading a portion of a lookup table (LUT) containing converted data elements into a lookaside buffer;

fetching a stream of data elements using a memory access engine;

replacing each data element in the stream of data elements with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to form a stream of converted data elements; and

propagating the stream of converted data elements from the memory access engine to a data processor.

2. The method of claim 1, wherein the lookaside buffer is dedicated for use by a first streaming engine, and wherein preloading the portion of the lookup table uses the first streaming engine to preload the LUT buffer.

3. The method of claim 2, wherein the memory access engine is a second streaming engine having a first in first out (FIFO) buffer, wherein propagating the stream of converted data elements includes storing a portion of the converted stream of data elements in the FIFO buffer.

4. The method of claim 1, further comprising:

operating the lookaside buffer as a cache;

detecting a miss when a requested converted data element is not present in the lookaside buffer; and

generating an access to a higher-level memory to retrieve the missing converted data element.

5. The method of claim 4, wherein detecting a miss detects more than one miss in parallel, and wherein generating an access generates multiple respective accesses to the higher memory.

6. The method of claim 5, wherein the multiple respective accesses occur in parallel.

7. The method of claim 1, further comprising:

mapping the contents of each data element of the stream of data elements to form a respective virtual address; and

accessing the lookaside buffer using the respective virtual addresses of the stream of data elements to obtain the respective converted data elements.

8. A method of operating a streaming engine, the method comprising:

operating a first streaming engine and a second streaming engine in a streaming mode for a first period to provide separate streams of data elements to a processor;

operating the first streaming engine and the second streaming engine in a ganged lookup table mode for a second period to provide a lookaside buffer holding a portion of a lookup table (LUT) of converted data elements; and

replacing each data element in a stream of data elements during the second period to form a stream of converted data elements to provide to the processor, wherein a respective converted data element is obtained from the LUT in the lookaside buffer according to a content of each data element.

9. The method of claim 8, further comprising:

mapping the contents of each data element of the stream of data elements to form a respective virtual address; and

accessing the lookaside buffer using the respective virtual addresses of the stream of data elements to obtain the respective converted data elements.

10. The method of claim 8, further comprising:

detecting a cache miss when a requested converted data element is not present in the lookaside buffer; and

accessing a higher-level memory to retrieve the missing converted data element.

11. The method of claim 10, wherein detecting a cache miss detects more than one cache miss in parallel, and wherein accessing the higher-level memory generates multiple respective accesses to the higher-level memory.

12. The method of claim 8, further comprising preloading a portion of the LUT into the lookaside buffer using the first streaming engine.

13. A data processing system comprising:

a processor to execute instructions;

a memory system;

a streaming engine coupled to the processor and to the memory system to fetch streams of data elements from the memory system; and

a lookaside buffer coupled to the streaming engine, the lookaside buffer containing a portion of a lookup table to replace a designated stream of data elements with a stream of converted data elements selected from the lookup table using a value of each data element in the designated stream of data elements.

14. The data processing system of claim 13, wherein the lookaside buffer is a cache memory, such that a cache miss is detected and resolved when a selected converted data element is not in the cache memory.

15. The data processing system of claim 13, wherein the lookaside buffer is a fully-associative cache memory, to detect more than one cache miss in parallel.

16. The data processing system of claim 13, wherein the streaming engine comprises:

an address generator to generate a stream of addresses;

control logic coupled to the address generator to request a stream of data elements from the memory system using the stream of addresses; and

a first in first out (FIFO) buffer coupled to the control logic, the FIFO buffer having an output coupled to the processor to provide the stream of data elements to the processor, wherein, while in a first mode, the FIFO buffer is configured to receive the stream of data elements from the memory system, and, while in a second mode, the FIFO buffer is configured to receive a stream of converted data elements selected from the lookup table.

17. The data processing system of claim 16, wherein the streaming engine is a first streaming engine, further comprising a second streaming engine that comprises:

a second address generator to generate a second stream of addresses;

second control logic coupled to the second address generator to request a second stream of data elements from the memory system using the second stream of addresses; and

a second FIFO buffer coupled to the second control logic, the FIFO buffer having an output coupled to the processor to provide the second stream of data elements to the processor, wherein, while in the first mode, the FIFO buffer is configured to receive the second stream of data elements from the memory system, and, while in the second mode, the FIFO buffer is configured to be the lookaside buffer.

18. The data processing system of claim 13, further comprising an element address mapper to convert contents of each data element of the stream of data elements to a respective virtual address to access the lookaside buffer.

19. The data processing system of claim 13, wherein the streaming engine includes a first-in-first-out (FIFO) buffer coupled to the processor to provide the stream of converted data elements to the processor.

20. The data processing system of claim 13, wherein the streaming engine is a direct memory access engine and is coupled to write the stream of converted data elements to the memory system.