PROCESSORS AND METHODS FOR PRIVILEGED CONFIGURATION IN A SPATIAL ARRAY
First Claim
1. A processor comprising:
- a plurality of processing elements;
an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and
a configuration controller coupled to a first subset and a second, different subset of the plurality of processing elements, the first subset of the plurality of processing elements having an output coupled to an input of the second, different subset of the plurality of processing elements according to configuration bits, wherein the configuration controller is to configure the interconnect network between the first subset and the second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when a privilege bit, separate from the configuration bits, is set to a first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value.
1 Assignment
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Accused Products
Abstract
Methods and apparatuses relating to privileged configuration in spatial arrays are described. In one embodiment, a processor includes processing elements; an interconnect network between the processing elements; and a configuration controller coupled to a first subset and a second, different subset of the plurality of processing elements, the first subset having an output coupled to an input of the second, different subset, wherein the configuration controller is to configure the interconnect network between the first subset and the second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset and the second, different subset when a privilege bit is set to a first value and to allow communication on the interconnect network between the first subset and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value.
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Citations
24 Claims
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1. A processor comprising:
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a plurality of processing elements; an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and a configuration controller coupled to a first subset and a second, different subset of the plurality of processing elements, the first subset of the plurality of processing elements having an output coupled to an input of the second, different subset of the plurality of processing elements according to configuration bits, wherein the configuration controller is to configure the interconnect network between the first subset and the second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when a privilege bit, separate from the configuration bits, is set to a first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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performing an operation of a dataflow graph with an interconnect network and a plurality of processing elements of a processor when an incoming operand set arrives at the plurality of processing elements, wherein the processor comprises the plurality of processing elements and the interconnect network between the plurality of processing elements, and the dataflow graph comprising a plurality of nodes is overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor according to configuration bits with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements; and configuring, with a configuration controller of the processor, the interconnect network between a first subset and a second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when a privilege bit, separate from the configuration bits, is set to a first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
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performing an operation of a dataflow graph with an interconnect network and a plurality of processing elements of a processor when an incoming operand set arrives at the plurality of processing elements, wherein the processor comprises the plurality of processing elements and the interconnect network between the plurality of processing elements, and the dataflow graph comprising a plurality of nodes is overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor according to configuration bits with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements; and configuring, with a configuration controller of the processor, the interconnect network between a first subset and a second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when a privilege bit, separate from the configuration bits, is set to a first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification