PROCESSORS, METHODS, AND SYSTEMS WITH A CONFIGURABLE SPATIAL ACCELERATOR HAVING A SEQUENCER DATAFLOW OPERATOR

• US 20190102338A1
• Filed: 09/30/2017
• Published: 04/04/2019
• Est. Priority Date: 09/30/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: TANG, JINJIE, FLEMING, KERMIN E., STEELY, SIMON C., GLOSSOP, KENT D., SUKHA, JIM
• Granted Patent: US 10,380,063 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/7892 Reconfigurable logic embedded in CPU, e.g. reconfigurable unit
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 8/452 Loops
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/4494 data driven

Abstract

Systems, methods, and apparatuses relating to a sequencer dataflow operator of a configurable spatial accelerator are described. In one embodiment, an interconnect network between a plurality of processing elements receives an input of a dataflow graph comprising a plurality of nodes forming a loop construct, wherein the dataflow graph is overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements and at least one dataflow operator controlled by a sequencer dataflow operator of the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements and the sequencer dataflow operator generates control signals for the at least one dataflow operator in the plurality of processing elements.

Claims

1. A processor comprising:

a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation;

a plurality of processing elements; and

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes forming a loop construct, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements and at least one dataflow operator controlled by a sequencer dataflow operator of the plurality of processing elements, and the plurality of processing elements is to perform a second operation when an incoming operand set arrives at the plurality of processing elements and the sequencer dataflow operator generates control signals for the at least one dataflow operator in the plurality of processing elements.

2. The processor of claim 1, wherein the dataflow operator comprises a pick operator.

3. The processor of claim 1, wherein the dataflow operator comprises a switch operator.

4. The processor of claim 1, wherein the plurality of processing elements is to perform the second operation when the incoming operand set arrives at the plurality of processing elements and the sequencer dataflow operator generates control signals for a first dataflow operator representing a first node of the dataflow graph and a second dataflow operator representing a second node of the dataflow graph.

5. The processor of claim 4, wherein the first dataflow operator representing the first node is a pick operator.

6. The processor of claim 5, wherein the second dataflow operator representing the second node is a switch operator.

7. The processor of claim 4, wherein the sequencer dataflow operator generates the control signals for the first dataflow operator representing the first node and the second dataflow operator representing the second node to perform a loop iteration of the loop construct in a single cycle of the processing elements.

8. The processor of claim 1, wherein the sequencer dataflow operator generates a next set of control signals for a loop iteration when both a base data token and a stride data token are received.

9. A method comprising:

decoding an instruction with a decoder of a core of a processor into a decoded instruction;

executing the decoded instruction with an execution unit of the core of the processor to perform a first operation;

receiving an input of a dataflow graph comprising a plurality of nodes forming a loop construct;

overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements and at least one dataflow operator controlled by a sequencer dataflow operator of the plurality of processing elements; and

performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements and the sequencer dataflow operator generating control signals for the at least one dataflow operator in the plurality of processing elements.

10. The method of claim 9, wherein the dataflow operator comprises a pick operator.

11. The method of claim 9, wherein the dataflow operator comprises a switch operator.

12. The method of claim 9, wherein the performing comprises performing the second operation of the dataflow graph with the interconnect network and the plurality of processing elements by the respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements and the sequencer dataflow operator generating control signals for a first dataflow operator representing a first node of the dataflow graph and a second dataflow operator representing a second node of the dataflow graph.

13. The method of claim 12, wherein the first dataflow operator representing the first node is a pick operator.

14. The method of claim 13, wherein the second dataflow operator representing the second node is a switch operator.

15. The method of claim 12, wherein the sequencer dataflow operator generates the control signals for the first dataflow operator representing the first node and the second dataflow operator representing the second node to perform a loop iteration of the loop construct in a single cycle of the processing elements.

16. The method of claim 9, further comprising the sequencer dataflow operator generating a next set of control signals for a loop iteration when both a base data token and a stride data token are received.

17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

decoding an instruction with a decoder of a core of a processor into a decoded instruction;

executing the decoded instruction with an execution unit of the core of the processor to perform a first operation;

receiving an input of a dataflow graph comprising a plurality of nodes forming a loop construct;

overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements and at least one dataflow operator controlled by a sequencer dataflow operator of the plurality of processing elements; and

performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements and the sequencer dataflow operator generating control signals for the at least one dataflow operator in the plurality of processing elements.

18. The non-transitory machine readable medium of claim 17, wherein the dataflow operator comprises a pick operator.

19. The non-transitory machine readable medium of claim 17, wherein the dataflow operator comprises a switch operator.

20. The non-transitory machine readable medium of claim 17, wherein the performing comprises performing the second operation of the dataflow graph with the interconnect network and the plurality of processing elements by the respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements and the sequencer dataflow operator generating control signals for a first dataflow operator representing a first node of the dataflow graph and a second dataflow operator representing a second node of the dataflow graph.

21. The non-transitory machine readable medium of claim 20, wherein the first dataflow operator representing the first node is a pick operator.

22. The non-transitory machine readable medium of claim 21, wherein the second dataflow operator representing the second node is a switch operator.

23. The non-transitory machine readable medium of claim 20, wherein the sequencer dataflow operator generates the control signals for the first dataflow operator representing the first node and the second dataflow operator representing the second node to perform a loop iteration of the loop construct in a single cycle of the processing elements.

24. The non-transitory machine readable medium of claim 17, wherein the method further comprises the sequencer dataflow operator generating a next set of control signals for a loop iteration when both a base data token and a stride data token are received.