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BINARY, TERNARY AND BIT SERIAL COMPUTE-IN-MEMORY CIRCUITS

  • US 20190102359A1
  • Filed: 09/28/2018
  • Published: 04/04/2019
  • Est. Priority Date: 09/28/2018
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a memory array of memory cells to store a binary weight matrix;

    a memory access circuit of bitlines having equal capacitance and wordlines driven with pulses of fixed duration to activate one or more memory cells in the memory array based on an input vector, wherein the memory access circuit to enable an activated bitcell in the memory array to cause a voltage drop in a bitline to which the activated bitcell is coupled, wherein the voltage drop is equivalent to voltage drops caused by other activated memory cells in the memory array; and

    a capacitor circuit coupled to the bitlines to accumulate bitline voltages after voltage drops into a voltage output, the voltage output to represent a dot product of the input vector and the binary weight matrix stored in the memory array.

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