MULTIPLE CONCURRENT MODULATION SCHEMES IN A MEMORY SYSTEM

• US 20190103143A1
• Filed: 05/11/2018
• Published: 04/04/2019
• Est. Priority Date: 10/02/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hasbun, Robert Nasry, Hollis, Timothy M., Wright, Jeffrey P., Gans, Dean D.
• Granted Patent: US 10,446,198 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2253 Address circuits or decoders
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

Claims

1. An apparatus, comprising:

a memory controller configured to communicate using a first signal type modulated using a first modulation scheme having at least three levels, and a second signal type modulated using a second modulation scheme having two levels;

a first memory die including a plurality of memory cells;

a first signal path coupled with the memory controller and the first memory die, the first signal path configured for the first signal type; and

a second signal path coupled with the memory controller and the first memory die, the second signal path configured for the second signal type.

2. The apparatus of claim 1, further comprising:

a second memory die including a plurality of memory cells;

a third signal path coupled with the memory controller and the second memory die, the third signal path configured for the first signal type; and

a fourth signal path coupled with the memory controller and the second memory die, the fourth signal path configured for the second signal type.

3. The apparatus of claim 1, wherein at least one of a signal of the first signal type or a signal of the second signal type comprises control data or storage data.

4. The apparatus of claim 1, wherein the memory controller is configured to concurrently transmit the first signal type and the second signal type.

5. The apparatus of claim 1, wherein the second signal type is modulated using a two-level modulation scheme representing at least two bits, and the first signal type is modulated using a pulse amplitude modulation (PAM) modulation scheme representing less than two bits.

6. The apparatus of claim 1, wherein at least one of the first signal path or the second signal path comprises a conductor in a through silicon via (TSV).

7. The apparatus of claim 1, further comprising:

a bus coupled with the memory controller and the first memory die, the bus configured to communicate the first signal type along the first signal path and the second signal type along the second signal path.

8. The apparatus of claim 7, wherein the first signal type is communicated along the first signal path and the second signal type is communicated along the second signal path during a rising edge or a falling edge associated with a system clock of the memory controller.

9. A method, comprising:

identifying first data to be communicated to a first memory die;

determining, from a plurality of modulation schemes, a first modulation scheme for the first data;

selecting a first signal path for communicating the first data based at least in part on determining the first modulation scheme from the plurality of modulation schemes; and

communicating a first signal modulated using the first modulation scheme to the first memory die using the first signal path.

10. The method of claim 9, further comprising:

identifying second data to be communicated to the first memory die;

determining, from the plurality of modulation schemes, a second modulation scheme for the second data, the second modulation scheme different from the first modulation scheme;

selecting a second signal path for the second data based at least in part on determining the second modulation scheme; and

communicating a second signal modulated using the second modulation scheme to the first memory die using the second signal path.

11. The method of claim 10, wherein:

the first modulation scheme comprises a non-return to zero (NRZ) modulation scheme; and

the second modulation scheme comprises a pulse amplitude modulation (PAM) modulation scheme representing at least three levels.

12. The method of claim 10, further comprising:

communicating the first signal modulated using the first modulation scheme to a second memory die coupled with the first memory die through a third signal path; and

communicating the second signal modulated using the second modulation scheme to the second memory die through a fourth signal path.

13. The method of claim 12, wherein the first memory die and the second memory die each comprise at least one of ferroelectric random access memory (FeRAM), a dynamic random access memory (DRAM), a NAND device, a NOR device, or a phase-change memory device.

14. The method of claim 13, wherein the second memory die comprises a different type of memory cell than the first memory die.

15. The method of claim 10, wherein communicating the first signal and the second signal is based at least in part on a timing of a system clock.

16. The method of claim 9, wherein the first modulation scheme is determined based at least in part on a type of the first data to be communicated to the first memory die.

17. The method of claim 9, wherein the first modulation scheme is determined based at least in part on an application type, a user input, a battery life of a device coupled with the first memory die, a power type associated with the device coupled with the first memory die, or a combination thereof.

18. An apparatus, comprising:

a first memory die including a plurality of memory cells;

a first signal path coupled with the first memory die;

a memory controller coupled with the first memory die and the first signal path, the memory controller operable to;

identify first data to be communicated to the first memory die;

determine, from a plurality of modulation schemes, a first modulation scheme for the first data;

select the first signal path for the first data based at least in part on determining the first modulation scheme from the plurality of modulation schemes; and

communicate a first signal modulated using the first modulation scheme to the first memory die using the first signal path.

19. The apparatus of claim 18, further comprising:

a second signal path coupled with the first memory die and the memory controller, the memory controller further operable to;

identify second data to be communicated to the first memory die;

determine, from the plurality of modulation schemes, a second modulation scheme for the second data different from the first modulation scheme;

select the second signal path for the second data based at least in part on determining the second modulation scheme; and

communicate a second signal modulated using the second modulation scheme to the first memory die using the second signal path.

20. The apparatus of claim 19, wherein the first signal is modulated using a non-return to zero (NRZ) modulation scheme and the second signal is modulated using a pulse amplitude modulation (PAM) modulation scheme, wherein the memory controller is operable to concurrently transmit the first signal and the second signal.

21. The apparatus of claim 19, wherein the memory controller is further operable to:

adjust a timing of the communication of the first signal and the second signal based at least in part on a timing of a system clock.

22. An apparatus, comprising:

a memory controller configured to communicate using a first signal type modulated using a first modulation scheme having at least three levels, and a second signal type modulated using a second modulation scheme having two levels;

a first memory die including a plurality of memory cells;

a second memory die including a plurality of memory cells;

a first signal path coupled with the memory controller and the first memory die, the first signal path configured for the first signal type; and

a second signal path coupled with the memory controller and the second memory die, the second signal path configured for the second signal type.

23. The apparatus of claim 22, wherein the second signal type is modulated using a non-return to zero (NRZ) modulation scheme and the first signal type is modulated using a pulse amplitude modulation (PAM) modulation scheme, wherein at least one of the first signal type or the second signal type comprises control data or storage data.

24. The apparatus of claim 22, wherein the memory controller is configured to concurrently transmit the first signal type to the first memory die and the second signal type to the second memory die.

25. The apparatus of claim 22, wherein the first memory die and the second memory die each comprise at least one of ferroelectric random access memory (FeRAM), a dynamic random access memory (DRAM), a NAND device, a NOR device, or a phase-change memory device.